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16.2. Overview
The Non-Volatile Memory (NVM) Controller manages all access to the
Non-Volatile Memories. The NVM
Controller controls all NVM timing and access privileges, and holds the
status of the NVM.
During normal execution the CPU will execute code from the code section
of the Flash memory (program
memory). When entering sleep and no programming operations are active,
the Flash memory is disabled
to minimize power consumption.
All NVM are mapped to the data memory. Application software can read the
NVM from the mapped
locations of data memory using load instruction with indirect
addressing.
The NVM has only one read port and, therefore, the next instruction and
the data can not be read
simultaneously. When the application reads data from NVM locations
mapped to the data space, the data
is read first before the next instruction is fetched. The CPU execution
is here delayed by one system
clock cycle.
Internal programming operations to NVM have been disabled and the NVM
therefore appears to the
application software as read-only. Internal write or erase operations of
the NVM will not be successful.
The method used by the external programmer for writing the Non-Volatile
Memories is referred to as
external programming. External programming can be done both in-system or
in mass production. The
external programmer can read and program the NVM via the Tiny
Programming Interface (TPI).
In the external programming mode all NVM can be read and programmed,
except the signature and the
calibration sections which are read-only.
NVM can be programmed at 5V, only.