ATXmega DMA mit DAC funktioniert nicht richtig

#define SYMBOL_BUFFER_SIZE  32

const uint16_t sineLUT[SYMBOL_BUFFER_SIZE * 2] =

{

  // 100%

  0x800,0x98f,0xb0f,0xc71,0xda7,0xea6,0xf63,0xfd8,

  0xfff,0xfd8,0xf63,0xea6,0xda7,0xc71,0xb0f,0x98f,

  0x800,0x670,0x4f0,0x38e,0x258,0x159,0x9c,0x27,

  0x0,0x27,0x9c,0x159,0x258,0x38e,0x4f0,0x670,

  0x800,0x98f,0xb0f,0xc71,0xda7,0xea6,0xf63,0xfd8,

  0xfff,0xfd8,0xf63,0xea6,0xda7,0xc71,0xb0f,0x98f,

  0x800,0x670,0x4f0,0x38e,0x258,0x159,0x9c,0x27,

  0x0,0x27,0x9c,0x159,0x258,0x38e,0x4f0,0x670,  

};

void vInitDAC()

{

  DACB.CTRLA = DAC_CH0EN_bm;  // Enable CH0

  DACB.CTRLB = DAC_CH0TRIG_bm;  // AutoTrigger CH0

  DACB.CTRLC = 0x0;  // Refernece Voltage

  DACB.EVCTRL = DAC_EVSEL_0_gc;  // Event Channel 1

  DACB.CTRLA |= DAC_ENABLE_bm;

  PORTB.DIRSET = 0x04;

}

void vInitDMA()

{

  vInitDAC();

  // set TCC1 to 11024Hz overflow, actually 11019.2838Hz (-0.052% error)

  TCC1.CTRLA = 0; // stop if running

  TCC1.CNT = 0;

  TCC1.PER = 0xFFFF;

  EVSYS.CH0MUX = EVSYS_CHMUX_TCC1_OVF_gc; // trigger on timer overflow  

  // reset DMA controller

  DMA.CTRL = 0;

  DMA.CTRL = DMA_RESET_bm;

  while ((DMA.CTRL & DMA_RESET_bm) != 0);

  DMA.CTRL = DMA_CH_ENABLE_bm | DMA_DBUFMODE_CH01_gc; // double buffered with channels 0 and 1

  //Bei Double Buffering wird automatisch aus Channel 0 und 1 ein "Pair" gebildet. 

  //Siehe dazu AVR1304.P8

  // channel 0

  // **** TODO: reset dma channels

  DMA.CH0.REPCNT    = 0;

  DMA.CH0.CTRLA    = DMA_CH_BURSTLEN_2BYTE_gc | DMA_CH_SINGLE_bm | DMA_CH_REPEAT_bm; // ADC result is 2 byte 12 bit word

  DMA.CH0.CTRLB    = 0x1;

  DMA.CH0.ADDRCTRL  = DMA_CH_SRCRELOAD_TRANSACTION_gc | DMA_CH_SRCDIR_INC_gc | // reload source after every burst

  DMA_CH_DESTRELOAD_BURST_gc | DMA_CH_DESTDIR_INC_gc; // reload dest after every transaction

  DMA.CH0.TRIGSRC    = DMA_CH_TRIGSRC_TCC1_OVF_gc;

  DMA.CH0.TRFCNT    = SYMBOL_BUFFER_SIZE * 2; // always the number of bytes, even if burst length > 1

  DMA.CH0.DESTADDR0  = ((uint16_t)(&DACB.CH0DATA)>>0) & 0xFF;

  DMA.CH0.DESTADDR1  = ((uint16_t)(&DACB.CH0DATA)>>8) & 0xFF;

  DMA.CH0.DESTADDR2  = 0;

  DMA.CH0.SRCADDR0  = ( (uint16_t) (&sineLUT[0]) >> 0) & 0xFF;

  DMA.CH0.SRCADDR1  = ( (uint16_t) (&sineLUT[0]) >> 8) & 0xFF;

  DMA.CH0.SRCADDR2  = 0;

  // channel 1

  DMA.CH1.REPCNT    = 0;

  DMA.CH1.CTRLA    = DMA_CH_BURSTLEN_2BYTE_gc | DMA_CH_SINGLE_bm | DMA_CH_REPEAT_bm; // ADC result is 2 byte 12 bit word

  DMA.CH1.CTRLB    = 0x1;

  DMA.CH1.ADDRCTRL  = DMA_CH_SRCRELOAD_TRANSACTION_gc  | DMA_CH_SRCDIR_INC_gc | // reload source after every burst

  DMA_CH_DESTRELOAD_BURST_gc  | DMA_CH_DESTDIR_INC_gc; // reload dest after every transaction

  DMA.CH1.TRIGSRC    = DMA_CH_TRIGSRC_TCC1_OVF_gc;

  DMA.CH1.TRFCNT    = SYMBOL_BUFFER_SIZE * 2;

  DMA.CH1.DESTADDR0  = ((uint16_t)(&DACB.CH0DATA)>>0) & 0xFF;

  DMA.CH1.DESTADDR1  = ((uint16_t)(&DACB.CH0DATA)>>8) & 0xFF;

  DMA.CH1.DESTADDR2  = 0;

  DMA.CH1.SRCADDR0  = ( (uint16_t) (&sineLUT[0]) >> 0) & 0xFF;

  DMA.CH1.SRCADDR1  = ( (uint16_t) (&sineLUT[0]) >> 8) & 0xFF;

  DMA.CH1.SRCADDR2  = 0;

  DMA.CH0.CTRLA    |= DMA_CH_ENABLE_bm;

  TCC1.CTRLA      = TC_CLKSEL_DIV1024_gc; // start timer, and in turn ADC

}