ESP32C3 > PLL

#define SYSTEM_BASE_ADDR                0x600C0000

#define SYSTEM_CPU_PER_REG              (*(volatile uint32_t*)(SYSTEM_BASE_ADDR + 0x0008))

#define SYSTEM_PLL_FREQ_SEL             1<<2

#define SYSTEM_CPU_PERIOD_SEL           0

#define SYSTEM_SYSCLK_REG               (*(volatile uint32_t*)(SYSTEM_BASE_ADDR + 0x0058))

#define SYSTEM_SOC_CLK_SEL_PLL_CLK      1<<10ul

void setup() {

  SYSTEM_CPU_PER_REG = (SYSTEM_PLL_FREQ_SEL | SYSTEM_CPU_PERIOD_SEL);

  SYSTEM_SYSCLK_REG = SYSTEM_SOC_CLK_SEL_PLL_CLK; 

  GPIO_ENABLE_REG |= 1<<0;

}

void loop() 

{

  GPIO_OUT_W1TS_REG = 1<<0;

  GPIO_OUT_W1TC_REG = 1<<0;

}