I am working in a VHDL project and I have to use the DDR2 memory
(MT47H64M16-25E) of the Atlys Spartan 6. I have already generated the
MCB with the MIG (ISE Design Suite 14.2). The configuration I have used
is in the attachments.
In order to test the MCB (Memory Control Block) on the board, I have
implemented my own top-level block (OnBoard_TB.vhd) and instantiated the
top level that the MIG had generated. I tried to make a simple
write/read without success, so I decided to test firstly every signal.
The calib_done goes high at the really begining, but then the signal
seems to be changing all the time and to do something strange. Just to
check the calib_done signal, I wrote this process:
calib_process : process
variable calib_times : integer := 0;
begin
wait until c3_calib_done'event and c3_calib_done = '1';
calib_times := calib_times + 1;
if calib_times > 10 then
leds(0) <= '1';
leds(7 downto 1) <= "0000000";
end if;
end process calib_process;
And the led went on. That means that the calib_done signal is changing
to low and high all the time. Is that correct? Should not be always high
after reaching a succesful calibration? I am just checking the signals
because I could not write and read what I had already written.
I just do not know if the MCB does not work properly or I am doing
something wrong. It would be really helpful if somebody could tell me if
I am doing something wrong, or send me an example of write/read with the
DDR2.
**You can find my entire project (also the UCF file) in the attachments.
Thank you very much.
