STM32F4 STM32L152: DAC Ausgabe DDS Spannungseinbruch

#include "stm32l1xx.h"

#include "timer.h"

#define SZ 1024

#define ML (4294967296 / SZ)

#define BS 200

#define SPS 60000

short sample[SZ] ={

    [...]

};

unsigned short DMAB0[BS];

unsigned short DMAB1[BS];

unsigned long long dwFreq = 55;

struct sTon{

  unsigned long wPos;

  unsigned long wVol;

  unsigned long wStepsize;

};

volatile struct sTon aoToene[10];

#define CALC(a) (sample[aoToene[(a)].wPos/ML]) * aoToene[(a)].wVol / 0x100

void calcbuffer(unsigned short * buffer){

  for(int x = 0; x < BS; x++){

    aoToene[0].wPos += aoToene[0].wStepsize;

    *buffer++ = CALC(0);

  }

}

void DMA1_Channel2_IRQHandler(void){

  DMA1->IFCR |= (1<<5);

  g_dwTime++;

  DMA1_Channel2->CCR &= ~1;

  if(DMA1_Channel2->CMAR == (unsigned long)&DMAB0[0]){

    DMA1_Channel2->CNDTR = BS;

    DMA1_Channel2->CMAR = (unsigned long)&DMAB1[0];

    DMA1_Channel2->CCR |= 1;

    calcbuffer(DMAB0);

  }else{

    DMA1_Channel2->CNDTR = BS;

    DMA1_Channel2->CMAR = (unsigned long)&DMAB0[0];

    DMA1_Channel2->CCR |= 1;

    calcbuffer(DMAB1);

  }

}

int main(void)

{

  RCC->CR |= 1;

  while(!(RCC->CR & 0b10));

  RCC->CFGR |= 0b01;

  while(!(RCC->CFGR & 0b0100));

  RCC->CFGR |= (0b000 << 11);      //APB2 Prescaler = 0

  RCC->CFGR |= (0b000 << 8);      //APB1 Prescaler = 0

  RCC->CFGR |= (0b0000 << 4);      //AHB Prescaler = 0

  RCC->AHBENR |= 1UL;            //GPIOA CLK

  RCC->AHBENR |= (1<<25);          //DMA1  CLK

  RCC->APB1ENR |= (1<<4);          //TIM6 CLK

  RCC->APB1ENR |= (1UL << 29);      //DAC CLK

  //GPIOA->OSPEEDR |= (0b11 << 2*4);

  GPIOA->MODER |= (0b11 << 2*4);      //PA4 analog

  TIM6->PSC   = 0;

  TIM6->ARR   = 16000000 / SPS - 1;

  TIM6->CR2 |= (1<<5);

  TIM6->CR1  |= 0x01;

  DAC->CR |= (1<<12);            //DMA enable

  DAC->CR |= 0b000100;          //TIM2 trigger

  DAC->CR |= 1;              //DAC ON

  DMA1_Channel2->CCR |= (0b11<<12);    //high priority

  DMA1_Channel2->CCR |= (0b01<<10);    //16 Bit peripherie

  DMA1_Channel2->CCR |= (0b01<<8);    //16 Bit memory

  DMA1_Channel2->CCR |= (1<<7);      //inc memory adress

  DMA1_Channel2->CCR |= (1<<4);      //mem to peripherie

  DMA1_Channel2->CCR |= (1<<1);      //TCIE enable

  DMA1_Channel2->CNDTR = BS;

  DMA1_Channel2->CMAR = (unsigned long)&DMAB0[0];

  DMA1_Channel2->CPAR = (unsigned long)&DAC->DHR12R1;

  DMA1_Channel2->CCR |= 1;

  NVIC->ICPR[DMA1_Channel2_IRQn/32] |= (1<<DMA1_Channel2_IRQn%32);

  NVIC->ISER[DMA1_Channel2_IRQn/32] |= (1<<DMA1_Channel2_IRQn%32);

  aoToene[0].wStepsize = dwFreq * SZ * ML / SPS;

  aoToene[0].wVol = 0xff;

  while(1){

  }

}