1 | #include "stm32l1xx.h"
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2 | #include "timer.h"
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3 |
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4 | #define SZ 1024
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5 | #define ML (4294967296 / SZ)
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6 | #define BS 200
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7 | #define SPS 60000
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8 |
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9 | short sample[SZ] ={
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10 | [...]
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11 | };
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12 |
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13 | unsigned short DMAB0[BS];
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14 | unsigned short DMAB1[BS];
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15 | unsigned long long dwFreq = 55;
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16 |
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17 | struct sTon{
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18 | unsigned long wPos;
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19 | unsigned long wVol;
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20 | unsigned long wStepsize;
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21 | };
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22 |
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23 | volatile struct sTon aoToene[10];
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24 |
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25 | #define CALC(a) (sample[aoToene[(a)].wPos/ML]) * aoToene[(a)].wVol / 0x100
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26 | void calcbuffer(unsigned short * buffer){
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27 | for(int x = 0; x < BS; x++){
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28 |
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29 | aoToene[0].wPos += aoToene[0].wStepsize;
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30 |
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31 | *buffer++ = CALC(0);
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32 | }
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33 | }
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34 |
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35 | void DMA1_Channel2_IRQHandler(void){
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36 | DMA1->IFCR |= (1<<5);
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37 | g_dwTime++;
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38 | DMA1_Channel2->CCR &= ~1;
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39 |
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40 | if(DMA1_Channel2->CMAR == (unsigned long)&DMAB0[0]){
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41 | DMA1_Channel2->CNDTR = BS;
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42 | DMA1_Channel2->CMAR = (unsigned long)&DMAB1[0];
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43 | DMA1_Channel2->CCR |= 1;
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44 |
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45 | calcbuffer(DMAB0);
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46 | }else{
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47 | DMA1_Channel2->CNDTR = BS;
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48 | DMA1_Channel2->CMAR = (unsigned long)&DMAB0[0];
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49 | DMA1_Channel2->CCR |= 1;
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50 |
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51 | calcbuffer(DMAB1);
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52 | }
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53 | }
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54 |
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55 |
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56 |
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57 | int main(void)
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58 | {
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59 |
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60 | RCC->CR |= 1;
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61 | while(!(RCC->CR & 0b10));
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62 | RCC->CFGR |= 0b01;
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63 | while(!(RCC->CFGR & 0b0100));
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64 | RCC->CFGR |= (0b000 << 11); //APB2 Prescaler = 0
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65 | RCC->CFGR |= (0b000 << 8); //APB1 Prescaler = 0
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66 | RCC->CFGR |= (0b0000 << 4); //AHB Prescaler = 0
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67 |
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68 | RCC->AHBENR |= 1UL; //GPIOA CLK
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69 | RCC->AHBENR |= (1<<25); //DMA1 CLK
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70 | RCC->APB1ENR |= (1<<4); //TIM6 CLK
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71 | RCC->APB1ENR |= (1UL << 29); //DAC CLK
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72 |
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73 | //GPIOA->OSPEEDR |= (0b11 << 2*4);
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74 | GPIOA->MODER |= (0b11 << 2*4); //PA4 analog
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75 |
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76 | TIM6->PSC = 0;
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77 | TIM6->ARR = 16000000 / SPS - 1;
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78 | TIM6->CR2 |= (1<<5);
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79 | TIM6->CR1 |= 0x01;
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80 |
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81 | DAC->CR |= (1<<12); //DMA enable
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82 | DAC->CR |= 0b000100; //TIM2 trigger
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83 | DAC->CR |= 1; //DAC ON
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84 |
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85 | DMA1_Channel2->CCR |= (0b11<<12); //high priority
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86 | DMA1_Channel2->CCR |= (0b01<<10); //16 Bit peripherie
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87 | DMA1_Channel2->CCR |= (0b01<<8); //16 Bit memory
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88 | DMA1_Channel2->CCR |= (1<<7); //inc memory adress
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89 | DMA1_Channel2->CCR |= (1<<4); //mem to peripherie
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90 | DMA1_Channel2->CCR |= (1<<1); //TCIE enable
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91 | DMA1_Channel2->CNDTR = BS;
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92 | DMA1_Channel2->CMAR = (unsigned long)&DMAB0[0];
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93 | DMA1_Channel2->CPAR = (unsigned long)&DAC->DHR12R1;
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94 | DMA1_Channel2->CCR |= 1;
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95 |
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96 | NVIC->ICPR[DMA1_Channel2_IRQn/32] |= (1<<DMA1_Channel2_IRQn%32);
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97 | NVIC->ISER[DMA1_Channel2_IRQn/32] |= (1<<DMA1_Channel2_IRQn%32);
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98 |
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99 | aoToene[0].wStepsize = dwFreq * SZ * ML / SPS;
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100 | aoToene[0].wVol = 0xff;
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101 |
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102 | while(1){
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103 | }
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104 | }
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