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// DMX transmission

ISR (USART_TXC_vect) {

 static unsigned char  dmxState = BREAK;

 static unsigned short curDmxCh = 0;

 if (dmxState == STOPPED) {

  if (artnet_dmxTransmitting == TRUE) {

   dmxState = BREAK;

  }

 } else if (dmxState == BREAK) {

  UBRR = (F_CPU / (50000 * 16L) - 1);

  UDR      = 0;                //send break

  dmxState = STARTB;

 } else if (dmxState == STARTB) {

  UBRR = (F_CPU / (250000 * 16L) - 1);

  UDR      = 0;                //send start byte

  dmxState = DATA;

  curDmxCh = 0;

 } else {

  _delay_us(IBG);

  UDR      = artnet_dmxUniverse[curDmxCh++];      //send data

  if (curDmxCh == artnet_dmxChannels) {

   if (artnet_dmxTransmitting == TRUE) {

    dmxState = BREAK;             //new break if all ch sent

   } else {

    dmxState = STOPPED;

   } 

  }

 }

}

// ----------------------------------------------------------------------------

// DMX reception

ISR (USART_RXC_vect) {

 static unsigned char  dmxState = 0;

 static unsigned short dmxFrame = 0;

 unsigned char status = UCSRA;   // status register must be read prior to UDR (because of 2 byte fifo buffer)

 unsigned char byte = UDR;     // immediately catch data from i/o register to enable reception of the next byte

 if ((byte == 0) && (status & (1<<FE))) {        // BREAK detected (Framing Error)

  dmxState = 1;

  dmxFrame = 0;

  if (artnet_dmxChannels > 0) {

   artnet_dmxInComplete = TRUE;

  }

 } else if (dmxFrame == 0) {              // Start code test

  if ((byte == 0) && (dmxState == 1)) {          // valid SC detected

   dmxState = 2;

  }

  dmxFrame = 1;

 } else {

  if ((dmxState == 2) && (dmxFrame <= MAX_CHANNELS)) {  // addressed to us

   if (artnet_dmxUniverse[dmxFrame - 1] != byte) {

    artnet_dmxUniverse[dmxFrame - 1] = byte;

  artnet_dmxInChanged = TRUE;

   }

   if (dmxFrame > artnet_dmxChannels) {

    artnet_dmxChannels = dmxFrame;

   }

  }

  dmxFrame++;

 }

}

#endif