ST24c04 - Nur erster Block lässt sich beschreiben

int Test_EEPROM (void)

{

  unsigned char eeprom_data;

  unsigned int address;

  int error_count = 0;

  // Block 0 beschreiben

  for (address = 0, eeprom_data = 0x00; address <= 0xff; address++, eeprom_data++)

  {

    EEPROM_Write (EEPROM_1, Block_0, address&0xFF, 1, (u8*)&eeprom_data);

  }

  // Block 1 beschreiben

  for (address = 0, eeprom_data = 0x00; address <= 0xff; address++, eeprom_data++)

  {

    EEPROM_Write (EEPROM_1, Block_1, address&0xFF, 1, (u8*)&eeprom_data);

  }

  eeprom_data = 0;    

  // Block 0 lesen

  for (address = 0; address <= 0xff; address++)

  {

    eeprom_data = (unsigned char)EEPROM_Read (EEPROM_1, Block_0, address&0xFF, 1);

    if (eeprom_data != address)

    {

      error_count++;

    }

  }

  eeprom_data = 0;

  // Block 1 lesen

  for (address = 0; address <= 0xff; address++)

  {

    eeprom_data = (unsigned char)EEPROM_Read (EEPROM_1, Block_1, address&0xFF, 1);

//    eeprom_data = *pTWI_RCV_DATA8;

    if (eeprom_data != address)

    {

      error_count++;

    }

  }

  return error_count;

}

void EEPROM_Write (u8 eeprom, u8 block, u8 address, u8 datasize, u8 *data)

{

  do

  {

    if (*pTWI_MASTER_STAT & ANAK)

      *pTWI_MASTER_STAT |= ANAK;    // Adress-NAK-Bit zurücksetzen

    xmt   = 0;

    mcomp = 0;

    TWI_TxPtr = data;          // Pointer auf Daten

    *pTWI_XMT_DATA8 = address;      // Adresse in FIFO laden

    EEPROM_Select (eeprom, block);    // EEPROM auswählen, hierzu müssen Daten im FIFO sein, ansonsten Fehler (siehe HW_Ref)

    TWI_Write (datasize + 1);      // Tx beginnen

    while((*pTWI_MASTER_STAT & BUSBUSY) || (*pTWI_MASTER_STAT & MPROG));  // Auf Tx_Ende warten

    TWI_Next_Cycle = 0;    

    while(!TWI_Next_Cycle);        // 10ms warten -> EEPROM Write Time!

  }while(*pTWI_MASTER_STAT & ANAK);    // Bei Adress-NAK nochmals versuchen

}

int EEPROM_Read (u8 eeprom, u8 block, u8 address, u8 datasize)

{

  unsigned char Rx_Data = 0;

  Restart_bytes_to_read = datasize;

  Restart_Flag = 1;

  *pTWI_XMT_DATA8 = address;      // Adresse in FIFO laden

  EEPROM_Select (eeprom, block);    // EEPROM auswählen, hierzu müssen Daten im FIFO sein, ansonsten Fehler (siehe HW_Ref)

  TWI_Write (1);            // Tx beginnen  

  TWI_RxPtr = (u8*)&Rx_Data;

  TWI_Next_Cycle = 0;

  while(!TWI_Next_Cycle);

  while((*pTWI_MASTER_STAT & BUSBUSY) || (*pTWI_MASTER_STAT & MPROG));  // Auf Tx_Ende warten

  return Rx_Data;

}

// Und hier die ISR

// TWI

  if (*pSIC_ISR & IRQ_TWI)

  {

    if (*pTWI_INT_STAT & MCOMP)          // Transfer Complete

    {

      *pTWI_INT_STAT |= MCOMP;        // Clear Interrupt 

      if (*pTWI_MASTER_CTL & RSTART)

      {

        *pTWI_MASTER_CTL &= ~RSTART;

        Restart_Flag = 0;

        *pTWI_MASTER_CTL |= ((Restart_bytes_to_read) << 6);

      }

      mcomp++;

    }

    if (*pTWI_INT_STAT & XMTSERV)        // Transfer IRQ

    {

      if ((*pTWI_MASTER_CTL & DCNT) > 40)    // Load next data if DCNT is > 1

        *pTWI_XMT_DATA8 = *TWI_TxPtr++;  // Otherwise data transfer will be completed in next cycle

      if (((*pTWI_MASTER_CTL & DCNT) == 0) && (Restart_Flag == 1))

      {

        *pTWI_MASTER_CTL |= RSTART;

        *pTWI_MASTER_CTL |= MDIR;

      }

      *pTWI_INT_STAT |= XMTSERV;        // Clear Interrupt 

      xmt++;

    }

    if (*pTWI_INT_STAT & MERR)

    {

      *pTWI_INT_STAT |= MERR;    // Clear Interrupt

      merr = *pTWI_MASTER_STAT;  // Save Master Status

    }

    if (*pTWI_INT_STAT & RCVSERV)      // Read IRQ

    {

      *pTWI_INT_STAT |= RCVSERV;      // Clear Interrupt

      *TWI_RxPtr++ = *pTWI_RCV_DATA8;    // Save received Byte

      rcv++;

    }

    ssync();

  }