PLL funktioniert nur im Debug - STM32F746G-Disco mit System Worckbench for STM32 als IDE

RCC->CFGR &= ~RCC_CFGR_SW_Msk; // activate hsi for main clock source

  while(RCC->CFGR & 0b11); // wait for hsi clock as main clock source is active

  RCC->CR &= ~(RCC_CR_PLLON_Msk); // stop pll

  while(RCC->CR & RCC_CR_PLLRDY); // wait for pll is stopped

  RCC->CR |= RCC_CR_HSEON; // start hse

  while(!(RCC->CR & RCC_CR_HSERDY)); // wait for hse get ready

  RCC->PLLCFGR &= ~((RCC_PLLCFGR_PLLQ_Msk) | (RCC_PLLCFGR_PLLP_Msk) | (RCC_PLLCFGR_PLLN_Msk) | (RCC_PLLCFGR_PLLM_Msk)); // reset parameters

  RCC->PLLCFGR |= (25<<RCC_PLLCFGR_PLLM_Pos) | (400<<RCC_PLLCFGR_PLLN_Pos) | (1<<RCC_PLLCFGR_PLLSRC_Pos) | (10<<RCC_PLLCFGR_PLLQ_Pos); // /M=25; *N=400; /P=2; HSE as Source

  RCC->CFGR |= (0b100<<RCC_CFGR_PPRE2_Pos) | (0b101<<RCC_CFGR_PPRE1_Pos); // APB2/2; APB1/4;

  RCC->CR |= RCC_CR_PLLON; // activate pll

  while(!(RCC->CR & RCC_CR_PLLRDY)); // wait for pll get ready

  RCC->CFGR |= RCC_CFGR_SW_PLL; // set pll for main clock source

  // ab hier wird nichts mehr ausgeführt...

  //while(!(RCC->CFGR & RCC_CFGR_SWS_PLL)); //wait for pll active