Taktfrequenz ATXmeaga128A1

//Oscillator auf 32Mhz einstellen PIN1 = OSC_RC32MEN wird gesetzt 

OSC.CTRL = 0x02;

// Wenn Oscillator stabil wird das Flag RC32MRDY

// gesetzt und 32Mhz können benutzt werden

while(!(OSC.STATUS & OSC_RC32MRDY_bm));

OSC.CTRL &=~ OSC_PLLEN_bm;  // PLL ausschalten

OSC.PLLCTRL  = OSC_PLLSRC_RC32M_gc | OSC_PLLFAC3_bm;  // Quelle und Multiplikator 8 einstellen 

OSC.CTRL  |= OSC_PLLEN_bm;    // PLL einschalten

while(!(OSC.STATUS & OSC_PLLRDY_bm));  // Warten bis PLL Ready

CCP = 0xD8; 

CLK.PSCTRL = 0x01;   // Prescaler C auf 2 stellen

CLK.CTRL = 0x04;     // Main Clk Source auf PLL stellen

//Oscillator auf 32Mhz einstellen PIN1 = OSC_RC32MEN wird gesetzt 

  OSC.CTRL = 0x02;

  // Wenn Oscillator stabil wird das Flag RC32MRDY

  // gesetzt und 32Mhz können benutzt werden

  while(!(OSC.STATUS & OSC_RC32MRDY_bm));

  OSC.CTRL &=~ OSC_PLLEN_bm;  // PLL ausschalten

  OSC.PLLCTRL  = OSC_PLLSRC_RC32M_gc | OSC_PLLFAC3_bm;  // Quelle und Multiplikator 8 einstellen 

  CLK.PSCTRL = 0x01;   // Prescaler C auf 2 stellen

  OSC.CTRL  |= OSC_PLLEN_bm;    // PLL einschalten

  while(!(OSC.STATUS & OSC_PLLRDY_bm));  // Warten bis PLL Ready

  CCP = 0xD8; 

  CLK.CTRL = 0x04;     // Main Clk Source auf PLL stellen

void sdram_init(void)

{

/* Initialize EBI. */

  EBI_Enable( EBI_SDDATAW_4BIT_gc,

              EBI_LPCMODE_ALE1_gc,

              EBI_SRMODE_ALE12_gc,

              EBI_IFMODE_3PORT_gc );

  PORTE.OUT |= (1<<PIN5);   // Dieser Punkt wird nicht erreicht

  /* Initialize SDRAM. (PER2X clock is 2MHz giving a 500ns clock cycle.) */

  EBI_EnableSDRAM( EBI_CS_ASIZE_8MB_gc,   /* 8 MB address space. */

                   SDRAM_ADDR,             /* Base address. */

                   false,                  /* 2 cycle CAS Latency. */

                   true,                   /* 12 Row bits. */

                   EBI_SDCOL_10BIT_gc,     /* 10 Column bits. */

                   EBI_MRDLY_2CLK_gc,      /* 2 cycle Mode Register Delay. (min 2CLK) */

                   EBI_ROWCYCDLY_1CLK_gc,  /* 1 cycle Row Cycle Delay. */

                   EBI_RPDLY_1CLK_gc,      /* 1 cycle Row to Pre-charge Delay. (min 37ns) */

                   EBI_WRDLY_2CLK_gc,      /* 2 cycle Write Recovery Delay. (1CLK + 7ns)*/

                   EBI_ESRDLY_1CLK_gc,     /* 1 cycle Exit Self Refresh to Active Delay. (min 67ns) */

                   EBI_ROWCOLDLY_1CLK_gc,  /* 1 cycle Row to Column Delay. (min 15ns) */

                   0x001F,                 /* 31 cycle Refresh Period (max 15.625us). */

                   0x00C8 );               /* 200 cycle Initialization Delay (min 100us). */

}

void EBI_Enable( EBI_SDDATAW_t sdramDataWidth,

                 EBI_LPCMODE_t lpcMode,

                 EBI_SRMODE_t sramMode,

                 EBI_IFMODE_t interfaceMode )

{

  /* These fields fill up the whole register, so we don't have to protect any bits with masks. */

  EBI.CTRL = (uint8_t) sdramDataWidth | lpcMode | sramMode | interfaceMode;

}

/* Initialize SDRAM. (PER2X clock is 64MHz giving a 15,625ns clock cycle.) */

  EBI_EnableSDRAM( EBI_CS_ASIZE_8MB_gc,   /* 8 MB address space. */

                   SDRAM_ADDR,             /* Base address. */

                   false,                  /* 2 cycle CAS Latency. */

                   true,                   /* 12 Row bits. */

                   EBI_SDCOL_10BIT_gc,     /* 10 Column bits. */

                   EBI_MRDLY_2CLK_gc,      /* 2 cycle Mode Register Delay. (min 2CLK) */

                   EBI_ROWCYCDLY_1CLK_gc,  /* 1 cycle Row Cycle Delay. */

                   EBI_RPDLY_3CLK_gc,      /* 3 cycle Row to Pre-charge Delay. (min 37ns) */

                   EBI_WRDLY_2CLK_gc,      /* 2 cycle Write Recovery Delay. (1CLK + 7ns)*/

                   EBI_ESRDLY_5CLK_gc,     /* 5 cycle Exit Self Refresh to Active Delay. (min 67ns) */

                   EBI_ROWCOLDLY_2CLK_gc,  /* 2 cycle Row to Column Delay. (min 15ns) */

                   0x001F,                 /* 31 cycle Refresh Period (max 15.625us). */

                   0x1900 );               /* 6400 cycle Initialization Delay (min 100us). */

// Taktsystem konfigurieren

    // externen 16MHz Quarz einschalten

    OSC.XOSCCTRL = OSC_XOSCSEL_XTAL_16KCLK_gc | OSC_FRQRANGE_12TO16_gc;// | OSC_X32KLPM_bm;

    OSC.CTRL |= OSC_XOSCEN_bm;

    while (!(OSC.STATUS & OSC_XOSCRDY_bm));

    // PLL Source = 16MHz ext. Quarz * 8 = 128 MHz  

    OSC.PLLCTRL = OSC_PLLSRC_XOSC_gc | (8 << OSC_PLLFAC_gp);

    OSC.CTRL |= OSC_PLLEN_bm;

    while (!(OSC.STATUS & OSC_PLLRDY_bm));

    // CLK-Prescaler A/1 B/2 C/2 -> 128MHz -> 64MHz -> 32MHz

    CCP_Write(&CLK.PSCTRL, CLK_PSADIV_1_gc | CLK_PSBCDIV_2_2_gc);

    // PLL nun als Systemclock auswählen

    CCP_Write(&CLK.CTRL, CLK_SCLKSEL_PLL_gc);

    // 2MHz und 32MHz RC abschalten

    OSC.CTRL &= ~(OSC_RC32MEN_bm | OSC_RC2MEN_bm | OSC_RC32KEN_bm);

    // nun CLK Einstellungen schützen

    CCP_Write(&CLK.LOCK, CLK_LOCK_bm);

void CCP_Write(volatile uint8_t* address, uint8_t value) {

  AVR_ENTER_CRITICAL_REGION();

  volatile uint8_t* tmpAddr = address;

#ifdef RAMPZ

  RAMPZ = 0;

#endif

  asm volatile(

    "movw r30,  %0"        "\n\t"

    "ldi  r16,  %2"        "\n\t"

    "out   %3, r16"        "\n\t"

    "st     Z,  %1"       "\n\t"

    :

    : "r" (tmpAddr), "r" (value), "M" (CCP_IOREG_gc), "i" (&CCP)

    : "r16", "r30", "r31"

    );

  AVR_LEAVE_CRITICAL_REGION();

}