VHDL Daten aus Datei

Stichwort: textio

Hier ein kleines Beispiel:

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LIBRARY ieee;

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USE ieee.std_logic_1164.all;

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USE ieee.std_logic_arith.all;

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USE ieee.std_logic_textio.all;                            -- Bibliotheken für TextIO / FileIO

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USE std.textio.all;

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ENTITY FileIO IS

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  PORT(

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    Start_fh         : OUT std_logic;                     -- Startet den FH, sobald alle Signale anliegen ( Sys_Clk abhängig ) -> DL_transmit_start

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    Done_fh          : IN  std_logic;                     -- Rückmeldung von FH, dass dessen Signale anliegen ( Sys_Clk ) -> DL_frame_arrive

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    DLL_err          : IN  std_logic;                     -- Fehler auf DLL Ebene

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    Sys_Clk          : IN  std_logic;                     -- Clock

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    IO_Addr_fh       : OUT std_logic_vector(4 downto 0);  -- Parameter Addr

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    IO_Data_fh_write : OUT std_logic_vector(7 downto 0);  -- Schreibdaten

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    IO_Data_fh_read  : IN  std_logic_vector(7 downto 0);  -- Lesedaten

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    IO_DL_Channel_fh : OUT std_logic_vector(1 downto 0);  -- DLL Channel

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    IO_DL_ftype_fh   : OUT std_logic_vector(1 downto 0);  -- Frame Type

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    DL_Event_fh      : IN  std_logic;                     -- DLL Event im Slave FH aufgetreten

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    RW_fh            : OUT std_logic                      -- RW_CMD

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    );

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END FileIO ;

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--

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ARCHITECTURE behaviour OF FileIO IS

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BEGIN

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  main : PROCESS

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  PROCEDURE read_file IS

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    VARIABLE break : boolean := false;                    -- Zur Ausgabe von Fehlermeldung, wenn Datei nicht lesbar

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    VARIABLE space : character;                           -- Leerzeichen

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    VARIABLE lin   : line;

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    VARIABLE nr    : string(1 to 2);                      -- Zeilen-Nummer

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    VARIABLE cmd   : string(1 to 2);                      -- CMD

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    VARIABLE addr  : std_logic_vector(4 downto 0);        -- Addresse

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    VARIABLE data  : std_logic_vector(7 downto 0);        -- Daten

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    FILE input_file : text;

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    BEGIN

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      file_open(input_file, "fileio_test_input.txt", read_mode);

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      WHILE(endfile(input_file) = false) LOOP

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        readline(input_file, lin);

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        read(lin, nr, break);

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        ASSERT break REPORT "Error reading input file!";

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        IF(nr(1 to 2) /= "--") THEN

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          read(lin, space);

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          read(lin, cmd);

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          read(lin, space);

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          hread(lin, addr);

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          read(lin, space);

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          hread(lin, data);

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          CASE cmd IS

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            WHEN "wr"   => RW_fh <= '1';             

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                           IO_Data_fh_write <= data;

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            WHEN "rd"   => RW_fh <= '0';               

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            WHEN OTHERS => NULL;

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          END CASE;

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          IO_Addr_fh <= addr;

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          WAIT UNTIL Sys_Clk'EVENT AND Sys_Clk = '1';     

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          Start_fh <= '1';

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          WAIT FOR 20ns;

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          Start_fh <= '0';

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        END IF;

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      END LOOP;

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      file_close(input_file);

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    END read_file;

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END ARCHITECTURE behaviour;

Die Eingabe-Datei hatte dabei das folgende Format.

--*-----------------------------------------------------------*
--* Format-Beispiel:                                          *
--*                                                           *
--* 53 wr 1C AA 2 0                                           *
--*  |  |  |  | | |                                           *
--*  +--------------> Nr. der Testzeile bzw. "--" als Kennung *
--*     |  |  | | |     für einen Kommentar                   *
--*     +-----------> CMD-Code (wr = write, rd = read)        *
--*        +--------> Paramter-Addr. (5 Bit)                  *
--*           +-----> Datenwert (8 Bit), bei wr der zu        *
--*             | |     schreibende Wert, bei rd der          *
--*             | |     erwartete Wert                        *
--*             +---> DL-Channel                              *
--*               +-> Frame Type                              *
--*************************************************************
00 wr 01 55 1 0
01 rd 01 55 1 0
02 wr 0E AC 1 0
03 rd 14 DC 1 0

Gruß zephyr

ranju@ins_amba:/srv/GHDL_training$ ghdl -a --ieee=synopsys FILE_IO.vhdl
FILE_IO.vhdl:32:24: no declaration for "print"
FILE_IO.vhdl:32:30: no declaration for "out_file"
FILE_IO.vhdl:33:24: no declaration for "print"
FILE_IO.vhdl:33:30: no declaration for "out_file"
FILE_IO.vhdl:36:53: no declaration for "lin"
FILE_IO.vhdl:38:39: no declaration for "break"
FILE_IO.vhdl:40:35: no declaration for "nr"
FILE_IO.vhdl:41:45: no declaration for "lin"
FILE_IO.vhdl:41:50: no declaration for "piece"
FILE_IO.vhdl:42:48: no declaration for "to_std_logic"
FILE_IO.vhdl:43:45: no declaration for "lin"
FILE_IO.vhdl:43:50: no declaration for "piece"
FILE_IO.vhdl:44:48: no declaration for "to_std_logic"
FILE_IO.vhdl:45:45: no declaration for "lin"
FILE_IO.vhdl:45:50: no declaration for "piece"
FILE_IO.vhdl:46:48: no declaration for "to_std_logic"
FILE_IO.vhdl:47:45: no declaration for "lin"
FILE_IO.vhdl:47:50: no declaration for "piece"
FILE_IO.vhdl:48:52: no declaration for "to_std_logic"
FILE_IO.vhdl:49:55: no declaration for "piece"
FILE_IO.vhdl:50:40: port "summe" can't be assigned
FILE_IO.vhdl:50:49: no declaration for "chr"
FILE_IO.vhdl:51:55: no declaration for "piece"
FILE_IO.vhdl:52:40: port "carry_out" can't be assigned
FILE_IO.vhdl:52:53: no declaration for "chr"
FILE_IO.vhdl:53:55: no declaration for "piece"
FILE_IO.vhdl:23:26:warning: procedure "read_file" is never referenced
/usr/lib/ghdl/bin/ghdl: compilation error


Das kam dabei raus.
Ach und wie stellt man synopsis automatisch ein?
Gruesse

Hallo

Hier der QUelltext

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_textio.all;                            -- 
Bibliotheken für TextIO / FileIO
USE std.textio.all;

ENTITY FileIO IS
  PORT(
    CLK         : IN  std_logic;                     -- Clock
    STEP    : OUT std_logic;                     -- RW_CMD
    OP_A    : OUT std_logic;
    OP_B    : OUT std_logic;
    CARRY_IN    : OUT std_logic;                     -- RW_CMD
    SUMME      : IN std_logic;                      -- RW_CMD
    CARRY_OUT   : IN std_logic                      -- RW_CMD
   );
END ENTITY;

ARCHITECTURE behaviour OF FileIO IS
BEGIN
  main: PROCESS

    PROCEDURE read_file IS
      VARIABLE lin_in    : line;    -- Zeile von Datei
      VARIABLE lin_out  : line;    -- Zeile in Datei
      FILE input_file   : text; -- Input
      FILE output_file   : text; -- Output

    BEGIN
      file_open(input_file, "Input.piece.log", read_mode); -- Open a 
file for reading the file.
      file_open(output_file, "Output.piece.log", write_mode); -- Open a 
file for reading the file.
      print(out_file, "## Output piece for all signals\n");
      print(out_file, "#\tStep\tsumme\tcarry_out");

      WHILE(endfile(input_file) = false) LOOP
        readline(input_file, lin); -- Read the line and save it in lin

        ASSERT break REPORT "Error reading input file!";

        IF(nr(1 to 2) /= "#") THEN -- If the line opens with # or ##, 
than skip the line!
          read(lin, piece); -- HIGH or LOW
          STEP <= to_std_logic(piece);
          read(lin, piece); -- Tab between left and step
          OP_A <= to_std_logic(piece);
          read(lin, piece); -- Tab between step and val
          OP_B <= to_std_logic(piece);
          read(lin, piece); -- Tab between step and val
          CARRY_IN <= to_std_logic(piece);
          write(lin_out, piece & "\t");
          SUMME <= chr(piece);
          write(lin_out, piece & "\n");
          CARRY_OUT <= chr(piece);
          write(lin_out, piece & "\n");
        ELSE NULL;
        END IF;

        writeline(output_file, lin_out);

      END LOOP;
      file_close(input_file);
      file_close(output_file);

    END PROCEDURE;
    begin
    end process;

END ARCHITECTURE;


Dieser Queltext wurde verwendet.

Joa... dieser Quellcode wurde oben aufgefuehrt. Aber du bist mit deinem 
Raten nicht weit entfernt:), obwohl ich schon weiss, was die einzelnen 
Funktionen tun und mit VHDL arbeite ich regelmaessig, aber FileIO ist 
mir vollkommen fremd.

Andere Frage: wo werden diese Packages installiert?

Ja, aber wie? Das sind Probleme die ich noch nicht hatte...