Verhalten Sim vs Post Fit Sim

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity QuadDecoder is

    Port ( CLK      : in std_logic;

           A      : in std_logic;

           B      : in std_logic;

        RST      : in std_logic;

           UP_DOWN  : out std_logic;

           C_ENABLE  : out std_logic;

           ERR      : out std_logic);

end QuadDecoder;

architecture VERH of QuadDecoder is

signal RST_SIG,A_OLD, B_OLD: std_logic;

begin

  QDecoder:  process(CLK, RST, A, B)

  variable DecPattern: std_logic_vector(3 downto 0);

  begin

    if RST = '1' then

      C_ENABLE  <= '0';

      UP_DOWN   <= '0';

      ERR    <= '0';

      A_OLD    <= '0';

      B_OLD    <= '0';

      RST_SIG  <= '1';

    elsif CLK = '1' and CLK'event then

      if RST_SIG = '1' and A = '0' and B = '0' then

        RST_SIG <= '0';  

      end if;

      if RST_SIG = '0' then

        DecPattern := A & B & A_OLD & B_OLD;

        A_OLD <= A;

        B_OLD <= B;

        case DecPattern is

          when "0000" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '0';

          when "0001" => UP_DOWN <= '1'; C_ENABLE <= '1'; ERR <= '0';

          when "0010" => UP_DOWN <= '0'; C_ENABLE <= '1'; ERR <= '0';

          when "0011" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '1';

          when "0100" => UP_DOWN <= '0'; C_ENABLE <= '1'; ERR <= '0';

          when "0101" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '0';

          when "0110" => UP_DOWN <= '1'; C_ENABLE <= '0'; ERR <= '1';

          when "0111" => UP_DOWN <= '1'; C_ENABLE <= '1'; ERR <= '0';

          when "1000" => UP_DOWN <= '1'; C_ENABLE <= '1'; ERR <= '0';

          when "1001" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '1';

          when "1010" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '0';

          when "1011" => UP_DOWN <= '0'; C_ENABLE <= '1'; ERR <= '0';

          when "1100" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '1';

          when "1101" => UP_DOWN <= '0'; C_ENABLE <= '1'; ERR <= '0';

          when "1110" => UP_DOWN <= '1'; C_ENABLE <= '1'; ERR <= '0';

          when "1111" => UP_DOWN <= '0'; C_ENABLE <= '0'; ERR <= '0';

          when others => null;

        end case;

      end if;

    end if;

  end process QDecoder;

end VERH;