es8k"S 3 sé ghe|eg a B B B > B LB S g A g e e i f k | 3 3 s 6 46 3 1 2 : . 3 ze 8 z 3 z a 3 aa a a i 383 2 2383s |3 a e g ane a geeee lsi 3, ooo e 3} seg 4 2 See esgsese|s |g ef3 g| 885 F 8 ai288|2 e 328 3 R R R agg U i] eeeeele | PL)" | 22 wan 38] R E G Sa |s 58 feo‘ | 222 ae< 38| Sessg | [22 kere 28
clock pulses for the result of an ADC cycle: SS in, a — — — — — — — r e W A I T t-SU TO- P» 2 OTt N oePA Tz- PP|+AW A I T - S T A T E t ST99 S T A R T 8 6 0 2 2 8 Figure 3.21 If the ADC control is in the WAIT-state a start can be generated and the ADC control starts the UP-phase. The timing of the UP<phase
