via the hardware, N D A C isgenerated. The T A (talker active) signal ishigh so that the input of D602 {aspecial GPIB device) islow. This means that a part of D602 acts as input and another part asoutput. ‘Outputs: NDAC, NRED, S R O D 6 0 2 Inputs: DAV, REN, ATN, EOI, IFC Also after ATN, the microcomputer
clock pulses for the result of an ADC cycle: SS in, a — — — — — — — r e W A I T t-SU TO- P» 2 OTt N oePA Tz- PP|+AW A I T - S T A T E t ST99 S T A R T 8 6 0 2 2 8 Figure 3.21 If the ADC control is in the WAIT-state a start can be generated and the ADC control starts the UP-phase. The timing of the UP<phase
