-
Datei
frames.vhd
process(rst, clk) variable do_shift : boolean; begin if rst='1' then s_q <= WAIT_FOR_SYNC; srg_q <= (others=>'0'); bclk1_q <= '0'; bclk2_q <= '0'; data_q <= '0'; fsync_q <= '0'; rising_bclk_q <= false; cnt_q <= 0; frame <= (others=>'0'); elsif rising_edge(clk) then do_shift := false; -- ext. Signale mit
-
Datei
VectorToBCD.vhd
:= idle; signal stelle : unsigned(3 downto 0) := "1101"; signal wert : unsigned(47 downto 0) := (others => '0'); begin process variable x : unsigned(47 downto 0):= (others => '0'); begin wait until rising_edge(clk); busy <= '0'; case state is when idle => -- wert <= to_integer(unsigned(vector)); wert <= unsigned(vector); if (start='1') then stelle <= 8; busy <= '1'; state<=calc; end if; when calc => x := wert; if (x>=90000000000000) then x:=x-90000000000000; bcd(stelle*4+3 downto stelle*4) <= x"9"; elsif (x>=80000000000000) then x:=x-80000000000000; bcd(stelle*4+3 downto stelle*4) <= x"
in „Lothar Millers VectorToBCD Koverter mit großen Zahlen“ · FPGA, VHDL & Co. ·
-
Datei
StateMachine.vhd
:= "000"; when OPIN_P2 => count_outi := "010"; state <= IPIN_P2; when IPIN_P2 => if SPG_TR2 = '0' then state <= RUN; else state <= ERR; end if; count_outi := "000"; when RUN => SECURE_STATE <= '1'; count_outi := "111"; when ERR => count_outi := "100"; when others => count_outi := "100"; state <= ERR; end case; end if; COUNT_OUT <= count_outi; end process; end ARCH_BEHAV; ---end Behavioral;
-
Datei
noteToneGenerator.vhd
<= not bitSignal; -- toggle bitSignal end if; end process soundGenerator ; waveOut <= "00000000" when bitSignal ='0' else amplitude ; note <= to_integer( unsigned(noteIn) ) ; -- note to frequency translation with note select prescaler <= NOTE_C4 when 0 , NOTE_D4 when 1 , NOTE_E4 when 2 , NOTE_F4 when 3 , NOTE_G4 when 4 , NOTE_A4 when 5 , NOTE_H4 when 6 , NOTE_C5 when others ; end Behavioral;
-
Datei
tst_bench_top.vhd
; --pullup i2c1_scl line process (scl) begin case scl is when '0' => scl_pullup_ctrl <= '0'; when others => scl_pullup_ctrl <= '1'; end case; end process; -- --pullup scl line -- process (scl,bool) -- begin -- if(bool='1') then -- scl_pullup_ctrl<='0'; -- else -- case scl is -- when '0' => -- scl_pullup_ctrl <= '0'; -- when others => -- scl_pullup_ctrl <= '1'; -- end case; -- end if; -- end process; --scl_pullup: process (scl_pullup_ctrl) --begin -- if scl_pullup_ctrl = '1' then
in „Probleme bei Lattice I2C EFB mit Wishbone Interface“ · FPGA, VHDL & Co. ·
-
PDF
DIY_Induction_Heater_Guide.pdf
could cause some extra wear on your button, and potentially cause it to burn out. ● My unit works when I turn it on, but flickers or turns off when I insert the DynaVap ○ Your unit is likely not getting enough power. You can usually resolve this by: ■ Removing some coils from your induction heater coil
in „Hilfe für Unwissenden! Wie steuer ich das?“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
50-555Circuits.pdf
SIMPLEST 555 OSCILLATOR The simplest 555 oscillator takes output pin 3 to capacitor C1 via resistor R1. When the circuit is turned on, C1 is uncharged and output pin 3 is HIGH. C1 charges via R1 and when Pin 6 detects 2/3 rail voltage, output pin 3 goes LOW. R1 now discharges capacitor C1 and when pin 2 detects
in „20 Volt Signal zu 12 Volt“ · Analoge Elektronik und Schaltungstechnik ·
-
PDF
50100125_2P_12000_3.7V_.pdf
Specification……………………………………………………..4 4. Battery Cell Performance Criteria……………………………..5 5. Storage and Others…………………………………………...6 6. Drawing (not to scale)……………………………………...….7 Handling Precautions and Guidelines……..……………..…8 1. Charging………………………………………………..……......8 2. Discharging……………………………………………………...8 3.
in „SAMMELBESTELLUNG: Lithium Polymer Zellen 3,7V/5Ah“ · Markt ·
-
PDF
50100125_6000_3.7V_.pdf
Specification……………………………………………………..4 4. Battery Cell Performance Criteria……………………………..5 5. Storage and Others…………………………………………...6 6. Drawing (not to scale)……………………………………...….7 Handling Precautions and Guidelines……..……………..…8 1. Charging………………………………………………..……......8 2. Discharging……………………………………………………...8 3.
in „SAMMELBESTELLUNG: Lithium Polymer Zellen 3,7V/5Ah“ · Markt ·
-
Datei
test_LCD.vhd
process (stand_zaehler, delay) begin if rising_edge (delay) and delay = '1' then case stand_zaehler is when 0 => initial <= "0000111001"; when 1 => initial <= "0000010100"; when 2 => initial <= "0001010101"; when 3 => initial <= "0001101101"; when 4 => initial <= "0001111000"; when 5 => initial <= "0000001111"; when 6 => initial <= "0000000001"; when 7 => initial <= "0000000110"; when others => initial <= "0000000000"; end case; end if; end process; data_out <= initial (7 downto 0); rs <= initial (9); rw <= initial
-
PDF
Samsung__35E.pdf
manufacturer, careful precautions should be taken to avoid damage of cell. 6. Others 6.1 Disassembly 6.1.1 The cell should not be dismantled from the battery pack. 6.1.2 Internal short-circuit caused by disassembly may lead to heat generation and/or venting. 6.1.3 When the electrolyte
in „INR18650-35E mit Labornetzteil laden“ · Mikrocontroller und Digitale Elektronik ·
-
Datei
dreh.vhd
; when Z11 => if (e = "10") then z <= Z10; cu := '1'; elsif (e = "01") then z <= Z01; cd := '1'; end if; when Z10 => if (e = "00") then z <= Z00; cu := '1'; elsif (e = "11") then z <= Z11; cd := '1'; end if
in „Signal von Drehgeber nicht erkannt“ · FPGA, VHDL & Co. ·
-
Datei
bcdshifter.vhd
; end process; bcd <= shift_reg; s_out <= converted(3); with shift_reg select converted <= "1000" when "0101", "1001" when "0110", "1010" when "0111", "1011" when "1000", "1100" when "1001", shift_reg when others; end arch;
-
Datei
top_bcd.vhd
; c <= '0'; d <= '1'; e <= '1'; f <= '0'; g <= '1'; when "0011" => a <= '1'; b <= '1'; c <= '1'; d <= '1'; e <= '0'; f <= '0'; g <= '1'; when "0100" => a <= '0'; b <= '1'; c <= '1'; d <= '0'; e <= '0'; f <= '1'; g <= '1'; when "0101" => a <= '1'; b <= '0'
in „Using the 7-segment Displays/ 7 Segment Anzeige“ · FPGA, VHDL & Co. ·
-
Datei
I2C.vhd
186 => I2C_SDAT <= data(8); WHEN 197 => I2C_SDAT <= data(7); WHEN 207 => I2C_SDAT <= data(6); WHEN 217 => I2C_SDAT <= data(5); WHEN 227 => I2C_SDAT <= data(4); WHEN 237 => I2C_SDAT <= data(3); WHEN 247 => I2C_SDAT <= data(2); WHEN
in „Cyclone II Starter Kit - Audio Codec“ · FPGA, VHDL & Co. ·
-
Datei
auswertung.vhd
" ELSe ausgabe<="001"; --wenn Frequenz größer als 82Hz, dann Ausgabe "zu hoch" END IF; WHEN "010000" => IF ist_freq < 110 then ausgabe<="100"; ELSIF ist_freq = 110 then ausgabe<="010"; ELSIF ist_freq > 110 then ausgabe<="001"; END IF; WHEN "001000" => IF ist_freq < 147 then ausgabe<="100";
-
PDF
ACclad_H-73247.pdf
sidual solvent (typical of polyimides) that may volatilize Safe Handling during press lamination.When drilling or routing parts Although DuPont is not aware of anyone developing with Pyralux AC flexible composites, provide adequate contact dermatitis when using Pyralux AC products, vacuum around the drill head to minimize worker expo- some individuals may be more sensitive than others. sure to dust. ® ® Anyone handling Pyralux AC should wash their hands Pyralux AC flexible composites do not contain polybro- with soap before eating, smoking or using restroom minated biphenyls (PBBs
-
PDF
doc8033.pdf
1) the data registers being written to or (2) from an incoming event from the XMEGA Event System. When triggered by data write operations, the conversion starts when the high byte register is updated. When the Event System is used, the conversion starts when an event arrives, not when the data registers
in „xmega DAC geht nicht im power save sleep?“ · Mikrocontroller und Digitale Elektronik ·
-
Datei
oneb_alu.vhd
not(B); else B_inv <= B; end if; G_AND <= A_inv and B_inv; G_OR <= A_inv or B_inv; case ALU_CTRL is when ADD_FUNC => temp := G_ADD; when SUB_FUNC => temp := G_ADD; when AND_FUNC => temp := G_AND; when OR_FUNC => temp := G_OR; when SLT_FUNC => temp := LESS; when NOR_FUNC => temp := G_AND; when others =>
-
PDF
CH9102DS1.PDF
to USB bus power supply, and when the loss of USB power is detected, CH9102 will turn off the USB and sleep (hang up). CH9102 provides VIO low-voltage protection mechanism when VBUS connects with resistor in series and used to control
in „CH9102X und Linux“ · Mikrocontroller und Digitale Elektronik ·
-
Datei
ram.vhdl
ram_t is array(0 to (2 ** addr'length - 1)) of std_logic_vector(7 downto 0); signal cells: ram_t := (others => "00000000"); signal d: std_logic_vector(data'range) := (others => '0'); begin data <= d when ce = '0' and wr = '1' else (others => 'Z'); process (clk) is variable ad: integer; begin if rising_edge
-
Datei
lcd_schnittstelle.vhd
lcd_enable = '0') THEN lcd_enable <= '1'; IF(char < 10) THEN char := char + 1; END IF; CASE char IS WHEN 1 => lcd_bus <= "1000110001"; WHEN 2 => lcd_bus <= "1000110010"; WHEN 3 => lcd_bus <= "1000110011"; WHEN 4 => lcd_bus <= "1000110100"; WHEN 5 => lcd_bus <= "1000110101"; WHEN 6 => lcd_bus <= "1000110110"; WHEN 7 => lcd_bus <= "1000110111"; WHEN 8 => lcd_bus <= "1000111000"; WHEN 9 => lcd_bus <= "1000111001"; WHEN OTHERS => lcd_enable <= '0'; END CASE; ELSE lcd_enable <= '0'; END IF; END IF; END PROCESS; END
-
Datei
ampel.vhd
elsif rising_edge(clk) then sekunde:=sekunde+1; if sekunde=dauer then sekunde:=0; case status is when -1=> colors <= "010"; dauer:=4; when 0 => colors <= "100"; dauer:=4; redflag<='1'; when 1 => colors <= "010"; dauer:=1; redflag<='0'; when 2 => colors <= "001"; dauer:=4; when 3 => colors <= "010"; dauer:=1; when others => end case; status <= status+1 mod 4; end if; end if; --end if; end process; end Behavioral;
in „Due to other FF/Latch trimming, FF/Latch Fehler“ · FPGA, VHDL & Co. ·
-
Datei
ManchesterEncoder.Vhd
clock_counter := "00000000000000000000"; end if; if ( data_counter = data_ref_cnt ) then case act_data_idx is when "0000" => data_reference <= data_input(1); when "0001" => data_reference <= data_input(2); when "0010" => data_reference <= data_input(3); when "0011" => data_reference <= data_input(4); when "0100" => data_reference <= data_input(5); when "0101" => data_reference <= data_input(6); when "0110" => data_reference <= data_input(7); when "0111" => data_reference <= parity; when others => data_reference <= '0'; end case; act_data_idx := act_data_idx
-
PDF
aMT-800480F-5.0-SAYD_G.pdf
of contrast ratio: The contrast ratio is defined as the following expression. Luminance measured when LCD on the "White" state Contrast ratio (CR) = Luminance measured when LCD on the "Black" state Note 5: Definition of Luminance Uniformity Active area is divided into 9 measuring areas (reference the
-
PDF
Datenblatt_Epson_S1D15G10_vom_Display_Controller.pdf
CCHR CCLW,CCLR WR, RD CS *2 CYC,CYC2 WR, RD D0 to D7 tS8 DH8 (Write) D0 to D7 ACC8 OH8 (Read) *1 is when access is made with WR and RD when CS is LOW. *2 is when access is made with CS when WR and RD are LOW. Ta=–40 to +85°C, DD=2.6 to 3.6V,DDI=2.6 to DD Signal Symbol Parameter Min. Max. Unit Measuringconditions
in „The Siemens S65 132x176, 65536 color display with AVR“ · Projekte & Code ·
-
PDF
S1D15G10.pdf
CCHR CCLW,CCLR WR, RD CS *2 CYC,CYC2 WR, RD D0 to D7 tS8 DH8 (Write) D0 to D7 ACC8 OH8 (Read) *1 is when access is made with WR and RD when CS is LOW. *2 is when access is made with CS when WR and RD are LOW. Ta=–40 to +85°C, DD=2.6 to 3.6V,DDI=2.6 to DD Signal Symbol Parameter Min. Max. Unit Measuringconditions
-
PDF
PiezoBasics.pdf
cause the material to develop an electric field, and vice versa. Working Principle of Piezo Buzzers When an alternating voltage is applied to the piezoceramic element, the element extends and shrinks diametrically. This characteristic of piezoelectric material is utilized to make the ceramic plate vibrate
in „Fluke 867B ungewöhnliches Problem.“ · Mikrocontroller und Digitale Elektronik ·
-
Datei
oneb_alu_msb.vhd
not(B); else B_inv <= B; end if; G_AND <= A_inv and B_inv; G_OR <= A_inv or B_inv; case ALU_CTRL is when ADD_FUNC => temp := G_ADD; when SUB_FUNC => temp := G_ADD; when AND_FUNC => temp := G_AND; when OR_FUNC => temp := G_OR; when SLT_FUNC => temp := LESS; when NOR_FUNC => temp := G_AND; when others =>
-
PDF
crc.pdf
nomial. Most initialize by assuming that the message has been preceded by cer- tain nonzero bits, others do no such initialization. Most transmit the bits within a byte least significant bit first, some most significant bit first. Most append the checksum least significant byte first, others most significant
-
PDF
DL_Anleitung_XO2_140416.pdf
" => G <= "1100"; when "1001" => G <= "1101"; when "1010" => G <= "1111"; when "1011" => G <= "1110"; when "1100" => G <= "1010"; when "1110" => G <= "1001"; when "1111" => G <= "1000"; when others => null; end case; end
in „Bildung des Zweierkomplements einer 4 Bit-Zahl“ · FPGA, VHDL & Co. ·
-
Datei
JobList_tb.vhd
DoneCommand ); clk <= not clk after 10 ns; -- 50 MHz tb : PROCESS BEGIN wait for 10 ns; case MemAdress is when "000000" =>CommandList <= x"0001000A"; when "000001" =>CommandList <= x"00020064"; when "000010" =>CommandList <= x"000300FF"; when "000011" =>CommandList <= x"000D01F4"; when "000100" =>CommandList <= x"000C0003"; when others =>CommandList <= x"00000000"; end case; END PROCESS; END;
-
Datei
FSM.vhd
CLK_F = '1'); if RESET = '1' or (CLK_R'event and CLK_R = '1') then State <= z0; else case State is when z0 => State <= z1; when z1 => --sig_ss_alt <= TxDone; if (TXDone = '1') then State <= z2; else State <= z1; end if; when z2 => State <= z1; when z3 => State <= z1; end case; end if; end process Z_SPEICHER; FSM: process begin wait until (CLK_F'event and CLK_F = '0'); case State is when z0 => senSPI <= '0'; senCordic <= '0'; senCompare <='0'; when z1 => senSPI <= '1'; senCordic <= '0'; senCompare <='0'; when z2 => senSPI <= '0'; senCompare <='1'; senCordic <= '1'; when z3 => senSPI
-
Datei
X_Latch.vhd
; signal RAMMoni : STD_LOGIC ; begin -- temp. Signal um Schreibweise zu vereinfachen MEMRD <= '0' when MREQ = '0' AND RD = '0' AND Reset = '1' ELSE '1'; MEMWR <= '0' when MREQ = '0' AND WR = '0' AND Reset = '1' ELSE '1'; RAMMoni <= '1' when IO16 ='1' OR IO17= '1' ELSE '0' ; -- Modul 1 Latch auf IO-PORT 14H Latchout <= (others => '0') when (Reset = '0') else DB when (ADR7 = x"14" AND IORQ = '0' AND WR = '0') else Latchout ; -- Modul 1 IO16H Register.. RAM ab 0..FFF IO16 <= '0' when (Reset = '0') else '1' when (ADR7 = x"16
in „VHDL Newbie -->Kontrolle VHDL COde“ · FPGA, VHDL & Co. ·
-
PDF
DOC1619.PDF
the human body. V Ss a high-voltage power supply, and R tCe series resistance of this power supply. When the switch S is connected to R C the capacitor is charged. When the switch S is connected to R ,Dthe capacitor is discharged through R D and the device under test, which is connected to or placed near
in „Spannungsstabilisierung/Entstörung“ · Analoge Elektronik und Schaltungstechnik ·
-
PDF
DOC1619_EMC_Design_Considerations.PDF
the human body. V Ss a high-voltage power supply, and R tCe series resistance of this power supply. When the switch S is connected to R C the capacitor is charged. When the switch S is connected to R ,Dthe capacitor is discharged through R D and the device under test, which is connected to or placed near
in „[Atmega8] Überempfindliche störanfälle Schaltung“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
DOC1619.PDF
the human body. V Ss a high-voltage power supply, and R tCe series resistance of this power supply. When the switch S is connected to R C the capacitor is charged. When the switch S is connected to R ,Dthe capacitor is discharged through R D and the device under test, which is connected to or placed near
in „Attiny im Dauerbetrieb“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
DOC1619.PDF
the human body. V Ss a high-voltage power supply, and R tCe series resistance of this power supply. When the switch S is connected to R C the capacitor is charged. When the switch S is connected to R ,Dthe capacitor is discharged through R D and the device under test, which is connected to or placed near
in „ATtiny 13 und 45 habens Programm vergessen“ · Mikrocontroller und Digitale Elektronik ·
-
Datei
SRAM_Operation.vhd
<= read_ram3; end if; when read_ram3 => if (SRAM_done = '0') then --check that SRAM is working internal_SRAM_exe <= '0'; state_reg <= modify1; end if; when modify1 => if (SRAM_done = '1') then --wait for completion read operation
in „Sram Simulation funktioniert nicht richtig“ · FPGA, VHDL & Co. ·
-
Datei
SRAM_Operation.vhd
<= read_ram3; end if; when read_ram3 => if (SRAM_done = '0') then --check that SRAM is working internal_SRAM_exe <= '0'; state_reg <= modify1; end if; when modify1 => if (SRAM_done = '1') then --wait for completion read operation
in „Sram Simulation funktioniert nicht richtig“ · FPGA, VHDL & Co. ·
-
Datei
main.vhd
<= addr(27 downto 24); next_state <= 10; when 10 => eprom_clk <= '1'; next_state <= 11; when 11 => eprom_clk <= '0'; -- 5. clock, Addresse 3 lad_out <= addr(23 downto 20); next_state <= 12; when 12 => eprom_clk <= '1'; next_state <= 13; when 13
-
Datei
main.vhd
<= addr(27 downto 24); next_state <= 10; when 10 => eprom_clk <= '1'; next_state <= 11; when 11 => eprom_clk <= '0'; -- 5. clock, Addresse 3 lad_out <= addr(23 downto 20); next_state <= 12; when 12 => eprom_clk <= '1'; next_state <= 13; when 13
-
Datei
segcontrol.vhd
= 0; case anzw is when "1111" => anzw <= "1110"; seg <= seg1; dp <= dpvec(0); when "1110" => anzw <= "1101"; seg <= seg2; dp <= dpvec(1); when "1101" => anzw <= "1011"; seg <= seg3; dp <= dpvec(2); when "1011" => anzw <= "0111"; seg <= seg4; dp <= dpvec(3); when "0111" => anzw <= "1110"; seg <= seg1; dp <= dpvec(0); when others => anzw <= "1111"; seg <= "1111111"; dp <= '1'; end case; else ancnt <= ancnt + 1; end if; end if; end process; end Behavioral;
-
PDF
en.DM00315319.pdf
independent from the V DD voltage VDDA : external power supply for analog VSS : ground IIH input current when input is 1 I : input current when input is 0 IL IOH: output current when output is 1 IOL: output current when output is 0 Ilkg leakage current IINJ injected current a. Arm is a registered trademark
in „STM32: 5 Volt tolerante Eingänge sind es nicht“ · Mikrocontroller und Digitale Elektronik ·
-
Datei
1.vhd
case; end process FOLGEZUSTANDSBERECHNUNG; ZUSTANDSAUSGABE: process (ZUSTAND) begin CASE ZUSTAND is when A => state <= "000"; when B => state <= "001"; when C => state <= "010"; when D => state <= "100"; when E => state <= "101"; when F => state <= "110"; end case; end process ZUSTANDSAUSGABE; ZUSTANDSAKTUALISIERUNG1
in „VHDL Text für die Ertönung eines 1 kHz Tons“ · FPGA, VHDL & Co. ·
-
PDF
Midas.pdf
display format, data length, etc. Set internal RAM addresses Perform data transfer with internal RAM Others instruction table at “Normal mode” Ø instruction table at “Extension mode” (when “EXT” option pin connect to VSS, the instruction set follow below table) 7.Instruction Description Clear all the display
in „Display mit SI7032: Wie Busy Flag lesen?“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
XPort_UG.pdf
Re-notification interval Indicates the time interval at which a new email message is sent to the recipient(s) when a single trigger event remains active. Trigger 2 Refer to Trigger 1 for details on completing these fields. Note: Each trigger is independent of the others. Each condition within an individual trigger
in „[V] einige gebrauchte Lantronix XPORT PRO IPv6 Module -LAN-Seriell Module (2St. für 26€)“ · Markt ·
-
PDF
XPort_UG.pdf
Re-notification interval Indicates the time interval at which a new email message is sent to the recipient(s) when a single trigger event remains active. Trigger 2 Refer to Trigger 1 for details on completing these fields. Note: Each trigger is independent of the others. Each condition within an individual trigger
in „[V] 2 gebrauchte Lantronix XPORT PRO Module -LAN-Seriell Module (beide 15€)“ · Markt ·
-
PDF
__XPort_UG__User_Guide_.pdf
Re-notification interval Indicates the time interval at which a new email message is sent to the recipient(s) when a single trigger event remains active. Trigger 2 Refer to Trigger 1 for details on completing these fields. Note: Each trigger is independent of the others. Each condition within an individual trigger
in „Lantronix XPort: Daten komplett auf UART“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
XPort_UG.pdf
Re-notification interval Indicates the time interval at which a new email message is sent to the recipient(s) when a single trigger event remains active. Trigger 2 Refer to Trigger 1 for details on completing these fields. Note: Each trigger is independent of the others. Each condition within an individual trigger
in „Xport zum steuern einer Lauftextanzeige“ · Mikrocontroller und Digitale Elektronik ·