Suchergebnisse für "when others"

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3880 Treffer für when others Suchergebnisse für "when others"

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  • Datei

    Neuron.vhd

    <= count_in + 1; if(count_in = INPUTS-1) then count_wait <= 0; Neuron_state <= pipe; Mult_a <= (others => '0'); Mult_b <= (others => '0'); end if; when pipe => Add_sum <= Add_result; count_wait <= count_wait + 1; if(count_wait = (2*LATENCY)-1) then Neuron_state <= finish; end if; when finish => int_Output <= Add_result; if(execute = '0') then Neuron_state <= idle; end if; when others => Neuron_state <= idle; end case; end if; end process; Output <= int_Output; Weight_Adr <= Layer_page & Layer_Input_Number; ready <= int_ready and not(execute); error <= Mult_underflow or Mult_overflow

    in „Pipeline MAC-Unit: Problem mit Latency“ · FPGA, VHDL & Co. ·

  • Datei

    frameerzeuger.vhd

    <= '1' when sig_count_tx_data = "0000" else '0'; sig_tx_data_register <= "00000011" when sig_send_bof = '1' else "10000011" when sig_send_eof = '1' else TX_FIFO_DATA_IN; --DATA_IO <= sig_tx_data_register; --sig_tx_fifo_empty

    in „INOUT Port - Richtung umschalten“ · FPGA, VHDL & Co. ·

  • Thread

    NIOS II mit eigenem Bauteil verbinden

    ; when x"03" => digital_o_reg <= as_writedata; when others => null; end case; end if; -------------------------------------------------------------------------

    as_read; if as_chipselect = '1' and as_read = '1' then case as_address is when x"00" => reg_readdata <= Input_register(31 downto 0); when x"01" => reg_readdata <= digital_i_reg; when x"02" => reg_readdata(15 downto 0) <= cBOARD_REVISION; when

    FPGA, VHDL & Co. ·Peer Ruudje · ·3 Antworten

  • Datei

    i2s_in.vhd

    : process (sclk_in, nreset) begin if nreset='0' then state_reg <= idle; right_reg <= (0 => '1', others => '0'); left_reg <= (0 => '1', others => '0'); ready <= '0'; else if rising_edge(sclk_in) then state_reg <= state_reg; case state_reg is when idle => ready <= '0'; if falling_edge(lrck_in) then state_reg

    in „von langsamer in schnellere taktdomain“ · FPGA, VHDL & Co. ·

  • Thread

    StateMachine - aber Warnung Gated Clock

    end if; end process; process (state) begin followingstate <= state; case state is when 1 => ... when 2 => ... ... when others => ... end case; end process; Vielleicht kann mir ja jemand weiterhelfen und sagen was ich falsch mache! Vielen Dank im Voraus Andi

    = '1') then state <= "00000"; elsif (rising_edge(clk)) then case state is when "00000" => ... state <= "0001"; when "00001" => ... state <= ... when others => ... state <= ... end case;

    FPGA, VHDL & Co. ·Andi · ·2 Antworten

  • Datei

    ddr.vhd

    time tWR: 15 ns when RecoverWrite => min.cmd <= CMD_NOP; min.ba <= "00"; min.adr(10) <= '0'; min.adr(9 downto 1) <= (others => '0'); if m.c = 1 then min.c <= 0; min.s <= PrechargeWait; else min.c <= m.c + 1; end if; ---

    in „Spartan-3E Starter Kit + DDR2“ · FPGA, VHDL & Co. ·

  • Thread

    State Machine mit warte-state

    else RD_EN_A <= '0'; RD_EN_B <= '0'; PDATA <= (others => 'Z'); end if; -- WARTE when WARTE => if (PCS1 = '0' and POEn = '0' and PRnW = '1') then RD_EN_A <= '0'; RD_EN_B <= '

    auch wirklich wartest. derzeit machst du eigentlich das selbe wie in LESEN... [vhdl] when WARTE => RD_EN_A <= '0'; RD_EN_B <= '0'; PDATA <= (others => 'Z'); if (PCS1 = '1') then -- deselektiert -> bereit für nächsten Lesezugriff

    FPGA, VHDL & Co. ·Andi · ·2 Antworten

  • Thread

    Defaults bei CASE-Anweisungen

    trx_dma_ch3_ena <= '1'; when others => trx_dma_ch4_adr <= inp_dma_trx_adr; trx_dma_ch4_dat <= inp_dma_trx_dat; trx_dma_ch4_cnt <= trx_dma_ch4_cnt+1;

    trx_dma_ch16_ena <= '0'; : case dma_channel_no is when "0000" => trx_dma_ch1_ena <= '1'; : when "0001" => trx_dma_ch2_ena <= '1'; : : : : : trx_dma_ch15_ena <= '1'; :

    FPGA, VHDL & Co. ·Messi · ·4 Antworten

  • Datei

    fifo.vhd

    w_ptr_reg; r_ptr_next <= r_ptr_reg; full_next <= full_reg; empty_next <= empty_reg; case wr_op is when "00" => -- no op when "01" => -- read if (empty_reg /= '1') then -- not empty r_ptr_next <= r_ptr_succ; full_next <= '0'; if (r_ptr_succ=w_ptr_reg) then empty_next <='1'; end if; end if; when "10" =

    in „UART Test Hilfe!“ · FPGA, VHDL & Co. ·

  • Datei

    bsp.txt

    Bsp.: CASE p1 IS WHEN "00000" => y <= '0'; WHEN "10000" => IF x >= z THEN y <= '1'; ELSE y <= '0'; END IF; WHEN OTHERS => y <= '0'; END CASE; Bsp.1: CASE p1 IS WHEN "00000" => y <= '0'; WHEN "10000" => IF x >= z THEN y <= '1'; ELSE y <= '0'; END IF; WHEN OTHERS => y <= '0'; END CASE; Bsp.2: y <= '0' CASE p1 IS WHEN "00000" => NULL; WHEN "10000" => IF x >= z THEN y <= '1'; END IF; WHEN OTHERS => NULL; END CASE;

    in „if innerhalb case?“ · FPGA, VHDL & Co. ·

  • Thread

    VGA Text Mode Problem

    green <= "0000"; blue <= "0000"; case zeilenpuffer1(signCounter) is when 0 => if ascii_a(bm_pixelCounter, bm_lineCounter) = '1' then green <= "1111"; else green <= "0000"; end if; when 1 => green <= "0000"; when OTHERS => green <= "0000"; end case; else red <= "0000"; green <= "0000"; blue <= "0000"; end if; ------------------------------------------------ end if;

    FPGA, VHDL & Co. ·Samuel J. · ·34 Antworten

  • Thread

    VHDL ALU ohne Libraries

    10": And, "11": Or process (iALUControl,iSrcA, iSrcB) begin case iALUControl is when "00" => -- A + B addBV(iSrcA, iSrcB, Result); when "01" => -- A - B bzw. (A + (-B)) --subBV(iSrcA, iSrcB, Result); when "10" => -- A AND B Result <= iSrcA and iSrcB; when "11" => -- A OR B Result <= iSrcA or iSrcB; when others => Result <= (others => '0'); end case; end process; Output: process (Result) begin oALUResult

    FPGA, VHDL & Co. ·David R. · ·4 Antworten

  • Datei

    VERSION_REGISTER.vhd

    ZERO) then -- if no CS for CPLD active, set Databus to high Z DATA <= (others =>'Z'); elsif (nRD'EVENT and nRD='0') then case CS is when (SHIFT_PATTERN sll START_CS_NR) => DATA <= CONV_STD_LOGIC_VECTOR(CPLD_VER, 8);--CPLD version register when (SHIFT_PATTERN sll (START_CS_NR +1))=> DATA <= CONV_STD_LOGIC_VECTOR(HW_VER, 8);--HW version register when (SHIFT_PATTERN sll (START_CS_NR +2))=> DATA <= CONV_STD_LOGIC_VECTOR(HW_TYPE, 8);--HW type register when others => DATA <= (others =>'Z'); end case; end if; end process; end BEHAVIOR;

    in „VHDL: case problem Quartus 9.0 <-> ModelSim“ · FPGA, VHDL & Co. ·

  • Datei

    prob.vhd

    write_counter > 100) then write_enable <= '0'; end if; end if; end Process; --b_puffer <= puffer(0) when read_enable = '1'; -- Simulation --Buffer_VAL <= puffer(write_counter) when read_enable = '1' else (others => '0'); -- Hardware DRAM Buffer_VAL <= "001001010110101000001101111111100011111000000000000000000000000001011010" when read_enable = '1' else (others => '0'); full_loc <= '1' when (write_counter = 100) else '0'; Full <= full_loc; -- dafür, ob RAM voll ist end Behavioral;

    in „ADC auslesen“ · FPGA, VHDL & Co. ·

  • Datei

    mmb.vhd

    CS2 SRAM 011 CS_Latch <= "011"; if AVR_AH(7 downto 2) = "000001" then case AVR_AH(1 downto 0) is when "01" => CS_Latch <= "111"; when "10" => CS_Latch <= "110"; when "11" => CS_Latch <= "101"; when others => NULL; end case; end if; end if; end process; process(AVR_WR, AVR_RD, AVR_AD, CS_Latch, Bank_Register

    in „128kByte Ram an AVR“ · Mikrocontroller und Digitale Elektronik ·

  • Datei

    MulAddSM.vhd

    getaktet. process begin wait until rising_edge(clk); -- spart die Sensitivity-List case (state) is when st0_idle => if (num1 /= (others=>'0') ) then state <= st0_idle; end if; when st1_calc1 => mu1_a <= num1; mu1_b <= num2; state <= st2_calc2; when st2_calc2 => result12 <= mu1_product; state <= st3_calc3; when st3_calc3 => mu1_a <= num3; mu1_b <= num4; state <= st4_calc4; when st4_calc4 => result34 <= mu1_product; state <= st5_calc5; when st5_calc5 => result <= result12 + result34; state <= st0_idle; end

    in „Latch bei Berechnung mittels FSM“ · FPGA, VHDL & Co. ·

  • Thread

    Altera CycloneI ATARI-FPGA

    clk_register) then if (reset_n_in = '0') then pia_crb2 <= '0'; pia_ddrb <= (others => '0'); pia_portb <= (others => '0'); else if (rw = '0') then case adr is when x"D301" => if (pia_crb2 = '0') then

    data_in; else pia_portb <= data_in; end if; when x"D303" => pia_crb2 <= data_in(2); when others => null; end case; end if; end if; end if; -- simulate pull-ups on inputs (ddrb is set to

    FPGA, VHDL & Co. ·mega-hz · ·22 Antworten

  • Datei

    ALU.txt

    port map (not a, b, '1', nicht_a_minus_b (n-1 downto 0), nicht_a_minus_b (n)); with s select z1 <= (others => '0') when "0000", '0' & a when "0001", '0' & b when "0010", a_negativ when "0011", b_negativ when "0100", '0' & (not a) when "0101", '0' & (not b) when "0110", a_plus_b when "0111", a_minus_b when "1000", b_minus_a when "1001", nicht_a_minus_b when "1010", '0' & (a or b) when "1011", '0' & (a and b) when "1100", '0' & (a xor b) when "1101", '0' & (not (a xor b)) when "1110", (others => '1') when others; cout <= z1(

    in „Einbinden mit component geht nicht.“ · FPGA, VHDL & Co. ·

  • Datei

    fsm.vhd

    S15 => count <= "1111"; if ain = '1' then yout <= '1'; else yout <= '0'; end if; when others => count <= "0000"; end case; end process; next_state_decode : process(state, ain) begin case(state) is when S0 => if ain = '1' then next_state <= S1; else next_state <= state; end if; when S1

    in „Probleme bei Vivado Tutorial mit State Machine“ · FPGA, VHDL & Co. ·

  • Datei

    NPI_Interface.vhd

    ; end if; when wait_for_falling => if (V_Sync_VideoIn = '0') then state_Set_WrAddrOffset <= wait_for_rising; end if; when others => state_Set_WrAddrOffset <= wait_for_rising; end case; end if; end process; -- Count

    in „ChipScope problem“ · FPGA, VHDL & Co. ·

  • Datei

    LA.vhd

    idle; signal dly : integer range 0 to 15 := 0; signal start_sr : std_logic_vector (3 downto 0) := (others=>'0'); signal result : std_logic_vector (3 downto 0) := (others=>'0'); begin -- Startknopf eintakten start_sr <= start_sr(2 downto 0)&START when rising_edge(CLK); process begin wait until rising_edge

    in „VHDL Verzögerung in process“ · FPGA, VHDL & Co. ·

  • Thread

    Tesbench synthetisierbar machen

    push2, push3); signal state : state_type := idle; signal counter : unsigned(8 downto 0) := (others => '0'); begin process begin wait until rising_edge(clk); case state is when idle => counter <= (others => '0'); if push(0) = '1' then state <= push0;

    ; end if; when push3 => counter <= counter + 1; cfg <= config4rom(to_integer(counter(8 downto 1))); cfgclk <= counter(0); if counter(8 downto 1) = 145 then state <=

    FPGA, VHDL & Co. ·Thomas · ·14 Antworten

  • Datei

    icache.vhd

    bit; variable b0Used : bit; begin if (reset_in_reset = '1') then read_state <= idle; read_addr <= (others => '0'); bufferIndex := 0; avalon_slave_readdata <= (others => '0'); avalon_slave_waitrequest <= '0'; clearValids; elsif (rising_edge(clock_in_clk)) then case read_state is when idle => if (avalon_slave_read

    in „warum Registers Added for RAM Pass-Through Logic wenn kein gleichzeitiger Zugriff?“ · FPGA, VHDL & Co. ·

  • Datei

    icache.vhd

    bit; variable b0Used : bit; begin if (reset_in_reset = '1') then read_state <= idle; read_addr <= (others => '0'); bufferIndex := 0; avalon_slave_readdata <= (others => '0'); avalon_slave_waitrequest <= '0'; clearValids; elsif (rising_edge(clock_in_clk)) then case read_state is when idle => if (avalon_slave_read

    in „warum Registers Added for RAM Pass-Through Logic wenn kein gleichzeitiger Zugriff?“ · FPGA, VHDL & Co. ·

  • Thread

    Byte lesen und schreiben beim SRam DE1.lb und ub

    Anbindung einer 8 Bit CPU an den 16 Bit SRAM auf dem DE1: [vhdl] RAM_D <= SRAM_DQ(7 downto 0) when A(0)='0' else SRAM_DQ(15 downto 8); SRAM_DQ(7 downto 0) <= CPU_DO when WR_n='0' and RAM_CS_n='0' else (others => 'Z'); SRAM_DQ(15 downto 8) <= CPU_DO when WR_n='0' and RAM_CS_n='0' else (others => 'Z'); SRAM_UB_N <= not A(0); SRAM_LB_N <= A(0); SRAM_ADDR(13 downto 0) <= A(14 downto 1); [/vhdl]

    FPGA, VHDL & Co. ·peter · ·7 Antworten

  • Thread

    VGA signal wird vom bildschirm nicht erkannt

    HCounter : process (clk25, reset) begin if reset = '1' then horizontal_counter <= (others => '0'); elsif clk25'event and clk25 = '1' then if EndOfLine = '1' then horizontal_counter <= (others => '0'); else horizontal_counter <= horizontal_counter + 1; end if; end if; end process HCounter; EndOfLine <= '1' when horizontal_counter = HTOTAL - 1 else '0'; VCounter: process (clk25, reset) begin if reset = '1' then vertical_counter <= (others => '0'); elsif clk25'event and clk25 = '1' then

    FPGA, VHDL & Co. ·Fragesteller · ·10 Antworten

  • Thread

    enable, wie richtig?

    a <= '0' & unsigned(x); -- b <= '0' & unsigned(y); -- c <= a + b; -- carry <= c(c'high) when enable = '1' else '-'; -- z <= std_logic_vector(c(n-1 downto 0)) when enable = '1' else (others => '-'); end Behavioral; [/vhdl]

    if enable = '1' then c <= '0' & unsigned(x) + '0' & unsigned(y); else c <= (others=>'0'); end if; end process; : [/vhdl] Das gibt zum guten Ende dann "nur" Kombinatorik. Und sowas >> carry <= c(c'high) when enable = '1' else '-'; '-', 'h', 'l', 'x'... kann die

    FPGA, VHDL & Co. ·daniel · ·3 Antworten

  • Datei

    UART_TX_8N1.vhd

    ; tick_counter <= (others=>'0'); tx<='0'; end if; if tick_counter=tick then tick_counter <= (others=>'0'); case state is when start => state <= data0; tx<=data_in(0); when data0 => state <= data1; tx<=data_in(1); when data1

    in „Anfängerfrage: Übertragung starten“ · FPGA, VHDL & Co. ·

  • Datei

    regf.vhd

    "11011" => D_OUT1 <= D_OUT; when "11100" => D_OUT1 <= D_OUT; when "11101" => D_OUT1 <= D_OUT; when "11110" => D_OUT1 <= D_OUT; when "11111" => D_OUT1 <= D_OUT; when others => D_OUT1 <= (others => 'U'); end case; end process read1;

    in „Registerspeicher“ · FPGA, VHDL & Co. ·

  • Thread

    Zwei Clockdomains, ein Signal.

    ,GREEN,BLUE,MUL_VAL); ENABLE<=MUL_VAL; IF(BT656_VIDEN='1')THEN CASE STATE IS WHEN GETCB=> MUL_EN<='0'; CB<=BT656_DATA; STATE<=GETY; STATE_FLAG<='1'; WHEN GETCR=> MUL_EN<='0'; STATE<=GETY; CR<=BT656

    ,GREEN,BLUE,MUL_VAL); ENABLE<=MUL_VAL; IF(BT656_VIDEN='1')THEN CASE STATE IS WHEN GETCB=> MUL_EN<='0'; CB<=BT656_DATA; STATE<=GETY; STATE_FLAG<='1'; WHEN GETCR=> MUL_EN<='0'; STATE<=GETY; CR<=BT656

    FPGA, VHDL & Co. ·GS · ·6 Antworten

  • Datei

    LVDS_TX.vhd

    <= "10011111"; blu <= "11111001"; process (lvds_clk, rst) begin if (rst = '0') then tx0_sreg <= (others => '0'); tx1_sreg <= (others => '0'); tx2_sreg <= (others => '0'); tx3_sreg <= (others => '0'); tft_clk <= '0'; state <= s0; h_cnt <= 0; v_cnt <= 0; elsif (lvds_clk'event and lvds_clk='1') then --

    in „LVDS seraliser“ · FPGA, VHDL & Co. ·

  • Thread

    Atmega SPI-Slave bleibt bekommt kein SPIF Signal und bleibt hängen

    spi_init() // Initialize pins for spi communication { /* Set MOSI SCK and SS output, all others input */ DDR_SPI = (1 << DD_MISO); DDR_SPI &= ~((1 << DD_MOSI) | (1 << DD_SCK) | (1 << DD_SS)); /* Enable SP */ SPCR = ((1<<SPE)| // SPI Enable (1<<SPIE

    // SPI Clock Rate FOSC/64 (0<<CPOL)| // Clock Polarity (0:SCK low / 1:SCK hi when idle) (0<<CPHA)); // Clock Phase (0:leading / 1:trailing edge sampling) SPSR = (1<<SPIF); // initialize }[/code] Ist bei der Initialisierung etwas verkehrt? Wäre suppi

    Mikrocontroller und Digitale Elektronik ·Mareike · ·13 Antworten

  • Datei

    ALU.vhd

    Sel, CIn, Oa, Ob) Variable TempAdd : std_logic_vector(32 downto 0); begin --Default Werte = Y <= (Others => '0'); COut <= '0'; TempAdd := (Others => '0'); Z <= '0'; case Sel is when "0000" => Y <= Ob; when "0001" => TempAdd := Oa + Ob + CIn; Y <= TempAdd(31 downto 0); COut <= TempAdd(32); if TempAdd(31

    in „Problem mit "Eigenbau" Pipeline ALU“ · FPGA, VHDL & Co. ·

  • Datei

    counter.vhd

    std_logic_vector(31 downto 0); begin process(clk,enable,reset,switches,count) begin case switches is when "0001" => q <= count(7 downto 0); when "0010" => q <= count(15 downto 8); when "0100" => q <= count(23 downto 16); when "1000" => q <= count(31 downto 24); when others => q <= (others => 'Z'); --Tristate end case; if reset = '1' then --Asynchroner Reset q <= (others => '0'); count <= (others => '0'); elsif rising_edge(clk) then if enable = '0' then --Synchroner Zähler mit enable count <= count +1; end if; end if; end process; end Behavioral;

    in „LED-Zähler mit Xilinx CPLD“ · FPGA, VHDL & Co. ·

  • Datei

    x7seg_vhd.vhd

    end process anode_selector; segment_mux : process begin wait until rising_edge(clk); anodes <= (others=>'0'); anodes(anode_cnt) <= '1'; case anode_cnt is when 0 => bcd_val<=dat(3 downto 0); when 1 => bcd_val<=dat(7 downto 4); when 2 => bcd_val<=dat(11 downto 8); when 3 => bcd_val<=dat(15 downto 12);

    in „vhdl Anfang mal wieder“ · FPGA, VHDL & Co. ·

  • Thread

    Probleme bei Lattice I2C EFB mit Wishbone Interface

    RESET = '1' then -- reset core WB_ADRESS <= x"4F"; WB_DATA_IN <= (others => '0'); WB_WRITE_EN <= '0'; WB_CYCLE <= '0'; WB_STROBE <= '0'; STATE <= START; else case STATE is when POR => WB_WRITE_EN <

    0'; WB_CYCLE <= '0'; WB_STROBE <= '0'; end if; when others => STATE <= STOP; end case; end if; end if; end process WB_to_I2C_FSM; [/vhdl]

    FPGA, VHDL & Co. ·lattice_user · ·20 Antworten

  • Thread

    conv_integer bei einem 8-bit Multiplexer

    y_int := conv_integer(a(4)); when "101" => y_int := conv_integer(a(5)); when "110" => y_int := conv_integer(a(6)); when "111" => y_int := conv_integer(a(7)); when others => null; end case; y <= y_int; end

    y <= a(to_integer(unsigned(sel)); [/vhdl] BTW: [vhdl] when others => null; [/vhdl] Das gibt in der Simulation ein Latch. In der Hardware ist es zum Glück egal, denn da gibt es nur '0' und '1' in einer Abfrage... BTW2: wozu der unnötige Umweg über y_int

    FPGA, VHDL & Co. ·Shark · ·1 Antworten

  • Thread

    VHDL Zahlen addieren und auf 7Seg ausgeben

    "1111101" when 6, -- 6 "0000111" when 7, -- 7 "1111111" when 8, -- 8 "1101111" when 9, -- 9 "1000000" when 10, -- KP+ "0110111" when 11, -- Enter "0111001" when 12, -- C "1111001" when 13, -- E "0000001" when others; --X -- PS2 Keyboard Scanner C1 : PS2_reader port map (mclk=>mclk, PS2C=>PS2C, PS2D=>PS2D, rst=>rst, Ps2Dout

    FPGA, VHDL & Co. ·Marko · ·1 Antworten

  • Datei

    Stickstoff.vhd

    -750mbar when others => Wert_Druck_Vorwahl <="000000000000"; end case; -- Aufnahme Wert Feuchtevorwahl (sel0, sel1, sel2) -- LSB -> MSB case S5 is when "011" => Wert_Feuchte_Vorwahl <="000100101000"; --entspricht

    in „Eingänger werden weg optimiert“ · FPGA, VHDL & Co. ·

  • Datei

    NEC_Decoder.vhd

    ; else state <= idle; end if; end if; when repeat => if (necsr = "11") then -- warten auf 1 --> erstes Bit cnt <= 0; if (cnt>rptlen) then -- Neue Übertragung state <= rx; bits <= (0=>'1', others=>'0'); else Repeated <= '1'; -- wiederholte Übertragung

    in „counter vhdl“ · FPGA, VHDL & Co. ·

  • Thread

    effizienter/kleiner, konfigurierbarer Frequenzteiler

    p_divide_sys_clk : PROCESS (NRES, CLK) BEGIN IF NRES = '0' THEN sys_clk_cnt <= (OTHERS => '0'); sys_clk_divide <= '0'; ELSIF rising_edge(CLK) THEN sys_clk_cnt <= sys_clk_cnt + 1; CASE FREQ_DIVIDE IS WHEN "11" => sys_clk_divide <= sys_clk_cnt(3); -- divide by 16 WHEN "10" => sys_clk_divide <= sys_clk_cnt(2); -- divide by 8 WHEN "01" => sys_clk_divide <= sys_clk_cnt(1); -- divide by 4 WHEN OTHERS => sys_clk_divide <= sys_clk_cnt(0); -- divide

    FPGA, VHDL & Co. ·Roman · ·3 Antworten

  • Datei

    sinus_574mhz.vhd

    data4 => DAC_CS <= '0'; SPI_MOSI <= 'X'; state_adc <= data5; when data5 => DAC_CS <= '0'; SPI_MOSI <= 'X'; state_adc <= data6; when data6 => DAC_CS <= '0'; SPI_MOSI <= 'X'; state_adc <= data7; when data7 => DAC_CS <= '0'; SPI_MOSI <= 'X'; state_adc <= data8; when

    in „SPI Communication mit FPGA“ · FPGA, VHDL & Co. ·

  • Datei

    counter.txt

    std_logic_vector (4 downto 0); begin if (DIR='1') then -- construction of a look-up-table for the next state when counting up case count is when "1001" => next_state<="0000"; when others => next_state<=count+1; end case; end if; if (DIR='0') then -- construction of a look-up-table for the next state when counting

    in „bad synchronous description“ · FPGA, VHDL & Co. ·

  • Thread

    Parallel to SPI Interface-Chip?

    THEN --reset system busy <= '1'; --set busy signal ss_n <= (OTHERS => '1'); --deassert all slave select lines mosi <= 'Z'; --set master out to high impedance rx_data <= (OTHERS => '0'); --clear receive data port state <= ready; --go to ready state when reset is exited ELSIF(clock'EVENT AND clock = '1') THEN CASE state IS --state machine WHEN ready => busy <= '0'; --clock out not busy signal

    Mikrocontroller und Digitale Elektronik ·holm · ·47 Antworten

  • Datei

    main.vhd

    WAIT_STATE_2; null; when WAIT_STATE_2 => NEW_STATE <= WAIT_STATE_3; null; when WAIT_STATE_3 => NEW_STATE <= LATCH_DATA_STATE; null; when LATCH_DATA_STATE => NEW_STATE <= LATCH_ADDR_STATE; null; when others => NEW_STATE <= RESET_STATE

    in „CPLD Stromaufnahme“ · FPGA, VHDL & Co. ·

  • Datei

    main.vhd

    signal read_bit :STD_LOGIC :='0'; begin P1:process(ASI_ASIC_IN_DUTY) begin case ASI_ASIC_IN_DUTY is when "01" => duty_cycle <=3300; when "10" => duty_cycle <=6600; when "11" => duty_cycle <=10000; when others => duty_cycle <=0; end case; end process P1; P2:process(CLK,reset) begin if (reset='1') then current_s

    in „InOut Port Problem“ · FPGA, VHDL & Co. ·

  • Datei

    main.vhd

    signal read_bit :STD_LOGIC :='0'; begin P1:process(ASI_ASIC_IN_DUTY) begin case ASI_ASIC_IN_DUTY is when "01" => duty_cycle <=3300; when "10" => duty_cycle <=6600; when "11" => duty_cycle <=10000; when others => duty_cycle <=0; end case; end process P1; P2:process(CLK,reset) begin if (reset='1') then current_s

    in „InOut Port Problem“ · FPGA, VHDL & Co. ·

  • Datei

    mmb.vhd

    011 512Kb SRAM CS_Latch <= "011"; if AVR_AH(7 downto 2) = "000001" then case AVR_AH(1 downto 0) is when "01" => CS_Latch <= "111"; when "10" => CS_Latch <= "110"; when "11" => CS_Latch <= "101"; when others => NULL; end case; end if; end if; end process; process(AVR_WR, AVR_RD, AVR_AD, CS_Latch, Bank_Register

    in „AVR Ethernet Platine“ · Mikrocontroller und Digitale Elektronik ·

  • Datei

    prbs_checker.vhd

    ; -- Internal expected PRBS state and status signal expected : std_logic_vector(15 downto 0) := (others => '0'); signal sync_reg : std_logic := '0'; signal err_cnt : unsigned(31 downto 0) := (others => '0'); signal loss_cnt : unsigned(31 downto 0) := (others => '0'); -- Simple sync state machine: require

    in „HW Link testen, auf datenintegrität, Frame loss“ · FPGA, VHDL & Co. ·

  • Datei

    Sinc_filt.vhd

    std_logic_vector(diff3_tmp(DATA_BIT_SIZE-2 downto 0)); DataOut_scale(15-(DATA_BIT_SIZE-1) downto 0) <= (others=>'0'); -- with diff3(DATA_BIT_SIZE-1) select -- DataOut <= (others => '1') when '1', -- --diff3(DATA_BIT_SIZE-2 downto DATA_BIT_SIZE-17) -- std_logic_vector(diff3(DATA_BIT_SIZE-2 downto DATA_BIT_SIZE-17)) -- when others; end generate DataBitSize_lt16; end Behavioral;

    in „Frage zum Theta Delta-Sigma AD“ · FPGA, VHDL & Co. ·