Suchergebnisse für "when others"

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3880 Treffer für when others Suchergebnisse für "when others"

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  • Thread

    Hilfe bei VHDL für Schieberegister mit einigen Extras

    if; if (rising_edge(SS)) then if (slave_nr = SLV_NR) then case chan_nr is when "000" => gain_1_s <= gain; when "001" => gain_2_s <= gain; when "010" => gain_3_s <= gain; when "011" => gain_4_s <= gain; when "100" => gain_5_s <= gain; when "101" => gain_6_s <= gain; when "110" => gain_7_s <= gain; when "111" => gain_8_s <= gain; --when others => gain_1_s <= "000"; end case; end if;

    FPGA, VHDL & Co. ·noips · ·15 Antworten

  • Datei

    i2c_low.vhd

    Send + Receive Ack data_int <= DATA; i2c_state <= ST_I2C_SEND_A; when "10" => -- I2C STOP i2c_state <= ST_I2C_STOP_A; when others => BUSY <= '0'; end case; end if; when ST_I2C_START_A => i2c_state <= ST_I2C_START_B; delay_flag <= '1'; delay_time <= DELAY_BIT; when ST_I2C_START_B

    in „I2C Master in VHDL“ · FPGA, VHDL & Co. ·

  • Datei

    sDFT.vhd

    <= '1'; -- update FiFo with new sample from ADC state <= load_st; else state <= wait_st; end if; when load_st => x_diff <= resize(signed(f_din) - x_0, x_diff'length); -- load twfarr from Twiddle_ROM (implicitely) r_rden <= '1'; -- read Xk_old from FBin_RAM state <= calc_st; when calc_st => for i in

    in „gh_fifo_sync_sr: loadless signals?“ · FPGA, VHDL & Co. ·

  • Thread

    Ratschlag / Verbesserung zu vhdl-Progrämmchen

    D_int select --Schiebestand an die Segmente DISP <= "1111001" when "00000001", "0100100" when "00000010", "0110000" when "00000100", "0011001" when "00001000", "0010010" when "00010000", "0000011" when "00100000", "1111000" when "01000000", "0000000" when "10000000", "1111111" when others; end Behavioral; [/vhdl]

    FPGA, VHDL & Co. ·Hartmut K. · ·13 Antworten

  • Datei

    ALU.vhd

    Sel, ERG_SUMME, ERG_AND, ERG_OR, ERG_RSHIFT, ERG_MULT) begin Cout <= '0'; case Sel is -- Addieren when "0001" => Y <= ERG_SUMME(31 downto 0); COut <= ERG_SUMME(32); -- Subtrahieren = Addieren mit gesetztem Carry! -- Wir brauchen dafür kein Extra Opcode --Multiplizieren when "0011" => Y <= ERG_MULT(31 downto 0); -- AND when "0100" => Y <= ERG_AND; -- OR when "0101" => Y <= ERG_OR; -- Rechtschift when "0111" => Y <= '0'&ERG_RSHIFT; -- Unbekannter Opcode = Ergebnis undefiniert when others => Y <= (others => '-'); end case

    in „Problem mit "Eigenbau" Pipeline ALU“ · FPGA, VHDL & Co. ·

  • Datei

    DUAL2BCD.vhd

    zaehler: std_logic_vector(3 downto 0); begin process (RESET, CLK) begin if RESET = '1' then z <= (others => '0'); DECIMAL <= (others => '0'); READY <= '0'; zaehler <= "0000"; current_state <= start_state; elsif CLK'event and CLK = '1' then case current_state is when start_state => if START = '1' then

    in „Binary To Decimal“ · FPGA, VHDL & Co. ·

  • Thread

    3 Achsen MEMS Beschleunigungs Sensorkit

    dort im Datenblatt steht. Ab Seite 20 im Datenblatt ist doch alles beschrieben : bit 0: RW bit. When 0, the data DI(7:0) is written into the device. When 1, the data DO(7:0)from the device is read. In latter case, the chip will drive SDO at the start of bit 8. bit 1: MS bit. When 0, the address

    (MSb first). In multiple read/write commands further blocks of 8 clock periods will be added. When MS bit is 0 the address used to read/write data remains the same for every block. When MS bit is 1 the address used to read/write data is incremented at every block.

    Mikrocontroller und Digitale Elektronik ·Andre R. · ·34 Antworten

  • Datei

    serdec.vhdl

    bitcnt<thr then data_serialized<='0'; bitcnt <= bitcnt+1; else -- bitcnt>=thr txbit<='1'; bitcnt<=(others=>'0'); data_serialized<='1'; end if; end if; end if; end process; advancestate: process (clk, state, data_serialized, writecommand, data_in) begin case state is when WAITFORDATA => if writecommand='1' then nextstate <= READDATA; end if; when READDATA => if data_in='1' then nextstate <= SERIALIZEDATA; end if; when SERIALIZEDATA => if data_serialized='1' then nextstate <= WAITFORDATA; end if; end case; if (state=READDATA or state=SERIALIZEDATA

    in „Anfängerproblem: Prozess einmal ablaufen lassen“ · FPGA, VHDL & Co. ·

  • Thread

    AEG induktionskochfeld HK654258 XB Relais Klickt, lüfter läuft und schaltet sich ab

    electric problem. I search the internet many times with no success. I was even more motivated when the second half of the induction died. I googled my problem once more and found this post. I was so glad when I get to the electronic board and saw I had the problem you described. A few minutes

    everyone to find. Could you please post the type, name and number of your Electrolux stove to help others find the solution?

    Analoge Elektronik und Schaltungstechnik ·Flip B. · ·27 Antworten

  • Datei

    main.vhd

    = 27; -- long wait -- when x"a" => next_state <= 1; -- error -- error <= '1'; when others => next_state <= 40; -- error error <= '1'; -- if addr = new_addr then -- new_addr <= new_addr + 1; -- addresse einen runter -- end if;

    in „EEprom über LPC ansteuern“ · FPGA, VHDL & Co. ·

  • Thread

    Flipflop und Latch

    Anfängerfehler? Das ist eher die Regel: Kombinatorik im Prozess, keine Defaultzuweisung (else... bzw. when others...) --> Latch Eine unvollständige Sensitivity-Liste dazu, und das Ganze verhält sich in der Simulation grundlegend anders als in der Realität.

    bitte jemand in VHDL übersetzen... [vhdl] : process (switch,a,b) begin case switch is when '1' => out1 <= a; when '0' => out2 <= b; end case; end process : [/vhdl] Hier ist sowohl out1 wie auch out2 nicht vollständig definiert, tauchen also nicht in jedem when-Pfad auf --> 2

    FPGA, VHDL & Co. ·Christian H. · ·26 Antworten

  • Thread

    Custom Type Zuweisung per Namen und Wert

    Aber bekomme ich mit der folgenden Beschreibung nicht noch einen: [vhdl] case count is when 0 => data_sel <= D0; when 1 => data_sel <= D1; when 2 => data_sel <= D2; when 3 => data_sel <= D3; when 4 => data_sel <= D4; when others => data_sel <= D0; end case;

    FPGA, VHDL & Co. ·Martin · ·3 Antworten

  • Datei

    adau1761_configuraiton_data.vhd

    "; when "0000011000" => data <= "101000000"; when "0000011001" => data <= "100010101"; when "0000011010" => data <= "100000001"; when "0000011011" => data <= "011111111"; when "0000011100" => data <= "101110110

    in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·

  • Datei

    Kaffeeautomat.vhd

    (others => '0'); begin -- Einsynchronisieren Pr50Csr <= Pr50Csr(3 downto 0)&Pruefer50Cent when rising_edge(clk); Pr1Esr <= Pr1Esr(3 downto 0) &Pruefer1Euro when rising_edge(clk); Pr2Esr <= Pr2Esr(3 downto 0) &Pruefer2Euro when rising_edge(clk); -- Flankenerkennung Pr50C <= '1' when Pr50Csr(4 downto 1) = "0111" else '0'; Pr1E <= '1' when Pr1Esr(4 downto 1) = "0111" else '0'; Pr2E <= '1' when Pr2Esr(4 downto 1) = "0111" else

    in „Hilfe für Code - VHDL“ · FPGA, VHDL & Co. ·

  • Datei

    FIFO.vhd

    write to FIFO -- push : set to 1 for 1 clk to write 1 data word to FIFO -- push must not be applied when "full" is true -- full flag: goes high when FIFO got full with last push -- overflow flag : goes high when a push occurs while "full" flag is set -- can only be reset by applying "reset" -- -- read

    in „FIFO Implementierung in BlockRAM“ · FPGA, VHDL & Co. ·

  • Datei

    top.vhd

    <= "0000"; m_axis_video_tid <= "0"; m_axis_video_tdest <= "0"; -- state <= STREAM_BEREIT; end if; when others => state <= STREAM_BEREIT; --m_axis_video_tvalid <= '0'; end case; end if; end if; end process; -- Auf den Simulationsausgang das gleiche legen wie auf den VFIFO (wird später auskommentiert)

    in „MIG mit AXI4 Interfacenauf Spartan 6“ · FPGA, VHDL & Co. ·

  • Thread

    VHDL Maxplus2 Library Compile Error

    wenigen Zeilen: [vhdl] signal reg : std_logic_vector (7 downto 0) := x"00"; : : reg <= inp when rising_edge(clk); outp <= x"00" when OE = 0 else reg; [/vhdl]

    to_integer(unsigned(A))) <= D; end if; Q(to_integer(unsigned(A))) <= D; else BITS <= (others => '0'); Q <= (others => '0'); if LE_n = '0' then Q(to_integer(unsigned(A))) <= D; end if; end if; end process; end;[/vhdl] Edit: Aber ja, weil es im FPGA keine Latches

    FPGA, VHDL & Co. ·Maximilian K. · ·23 Antworten

  • Thread

    Gray Code to 7-Segment

    process (gray) begin case gray is -- abcdefg abcdefg when "00000" => zehner <= "1111110"; einer <= "1111110"; -- 00 when "00001" => zehner <= "1111110"; einer <= "0110000"; -- 01 when "00011" => zehner <= "1111110"; einer <= "1101101"; -- 02 : when "10001" => zehner <= "0110000"; einer <= "0110000"; -- 62 when others => zehner <= "0011111"; einer <= "1111001"; -- 63 end process; [/vhdl] > um es vielleicht in ein CPLD XC9572

    FPGA, VHDL & Co. ·Peter Zz · ·5 Antworten

  • Thread

    Timing FT2232H

    then TXEFF<=TXE; end if; end process; if rising_edge(DCLK)then case(SSnd) is when WaitingForSendFlag => If AquisitionDone='1' then SSnd<=WaitForInitialTXELow; FinalAddress<=unsigned(WAddress); Counter<=unsigned(WAddress)+1; end if; when

    SSnd<=Done; else SSnd<=Send1; end if; end if; when WaitForResume => if TXEFF='0' then SSnd<=ResumeState; end if; when Done=> WR<='1'; when others => SSnd <=WaitingForSendFlag; end case; end if; [/vhdl

    FPGA, VHDL & Co. ·Christian · ·22 Antworten

  • PDF

    IFR14500EC-600mAh.pdf

    Model: IFR14500EC-600mAh 4 3. Specification 4 4. Battery Cell Performance Criteria 5 5. Storage and Others 7 6. Battery Cell Drawing (all unit in mm, not in scale) 7 Handling Precautions and Guideline 8 1. Charging 8 2. Discharging 8 3. Protection Circuit Module (PCM) 9 4. Storage 9 5. Others 9 Customer

    in „Externer Akku an digitales Heizkörperthermostat“ · Mikrocontroller und Digitale Elektronik ·

  • Datei

    SOB.vhd

    ReadyxSO <= std_logic_vector(to_unsigned(cnt,3)); -- end process FIR_comb ; -- ReadyxSO <= "000" when DataBufxD="0000" else -- "001" when DataBufxD="0001" or DataBufxD="0010" or DataBufxD="0100" or DataBufxD="1000" else -- "010" when DataBufxD="0011" or DataBufxD="0110" or DataBufxD="1100" or DataBufxD

    in „Mittelwertfilter“ · FPGA, VHDL & Co. ·

  • Datei

    bubble.vhd

    => '0'); signal addrb_d3 : std_logic_vector(5 downto 0) := (others => '0'); signal addrb_d4 : std_logic_vector(5 downto 0) := (others => '0'); signal dout_a : std_logic_vector(15 downto 0) := (others => '0'); signal din_a : std_logic_vector(15 downto 0) := (others

    in „RAM basierter Bubble Sort in VHDL“ · FPGA, VHDL & Co. ·

  • Datei

    AudioInterface.vhd

    std_logic; CLK_OUT : out std_logic ); end component; signal s_delay : std_logic_vector(11 downto 0) := (others => '0'); signal s_filter_input_data_l_16_bit : std_logic_vector(15 downto 0) := (others => '0'); signal s_filter_input_data_r_16_bit : std_logic_vector(15 downto 0) := (others => '0'); signal s_filtered_output_data_l

    in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·

  • Thread

    VHDL Prozess nur "anstupsen"

    -- irgendwas resetten falls notwendig state:=0; else case state is when 0 => if trigger='1' then state:=1; end if; when 1 => -- einmalig irgendwas machen state:= 2; when 2 => -- bleibt für immer in 2 when others => state:=0; end case; end if; end if; end if; [/vhdl] oder sowas: [vhdl] -- läuft einmal, bleibt dann stehen process(clk) variable flag : std_logic := '0';

    FPGA, VHDL & Co. ·Mark W. · ·15 Antworten

  • Datei

    sigmadelta.vhd

    end process; -- Erzeugen des D-FlipFlop zum Zwischenspeichern -- with clk select dIn_alt <= dIn_neu when '1', dIn_alt when others; Komperator: process (dIn_alt) -- Herausfiltern des MSBit -- begin alt_conv <= std_logic_vector(din_alt); dOut_read <= alt_conv (10); end process Komperator; Erzeugen: process (dOut_read) -- Erzeugen eines Vektors-- begin case dOut_read is when '0' => dOutm <= "0000000000"; when '1' => dOutm <= "1111111111"; when others => dOutm <= "0000000000"; end case; dOutm_conv <= signed (dOutm); end process Erzeugen; data_out <= dOut_read; -- Ausgeben

    in „Problem bei der Simulation (Buskonflikt)“ · FPGA, VHDL & Co. ·

  • Thread

    Zugriff auf gleiches Signal aus verschiedenen Prozessen?

    zwei einfache Schreibweisen: [vhdl] Foo : process(Selector) begin case Selector is when 1 => Address <= x"0123"; when 2 => Address <= x"4567"; when 3 => Address <= x"89AB"; when others => Address <= "ZZZZZZZZZZZZZZZZ"; end case; end process; [/vhdl] oder noch kürzer: [vhdl] Address <= x"0123" when Selector = 1 else x"4567" when Selector = 2 else x"89AB" when Selector = 3 else "ZZZZZZZZZZZZZZZZ"; [/vhdl]

    FPGA, VHDL & Co. ·Steffen Hausinger · ·31 Antworten

  • Datei

    FT2232H_minimal_A.vhd

    FT2232H------------------------------------------------- signal counter: unsigned(8 downto 0):=(others => '0'); signal new_burst: std_logic:='0'; signal fifo_miss: unsigned(3 downto 0):=(others => '0'); type fsm_fifo_type is(fifo_reset, fifo_check, fifo_write, fifo_wait); signal fsm_fifo: fsm_fifo_type

    in „FT2232H Sync FIFO“ · FPGA, VHDL & Co. ·

  • Datei

    Reg_bidirectional.vhd

    WRITE READ=0 WRITE=1 BUS_EN : IN STD_LOGIC:='0'; -- CHIP ENABLE BUS_BUSY : OUT STD_LOGIC:='0'; -- '1' WHEN REGISTER IS WRITING DATA TO GLOBAL BUS BUS_ADDR : IN STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0):=(OTHERS=>'0'); --BUS ADRESSE DOUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0):=(OTHERS=>'0'); --REGISTER DATA OUT DIN : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0):=(OTHERS=>'0'); -- REGISTER DATA IN BUS_DATA : INOUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0):=(OTHERS=>'Z'); --DATA OUTPUT TO CONTROLLER BUS_DATA_INPUT : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0):=(OTHERS=

    in „2 Clock Domains, signale verbinden“ · FPGA, VHDL & Co. ·

  • Datei

    clkgen.vhd

    11" => -- 3 Hz ClkLeft <= Clk3Hz; SignalLeft <= Clk3Hz; when others => ClkLeft <= PulseLeft; SignalLeft <= PulseLeft; end case; -- Erzeugung der Signale fuer Generator Right case ClkModeRight is when "00" => ClkRight <= PulseRight; -- Pulse SignalRight <= PulseRight

    in „Lauflicht mit vorgegbenen Clkgen“ · FPGA, VHDL & Co. ·

  • Thread

    Anzeigefehler in ISE 10.1 oder habe ich etwas übersehen?

    architecture MUX of CK_MUX is begin CMUX: process (CK_SEL, CK_IN) begin case CK_SEL is when "00" => CK_OUT <= CK_IN(0); when "01" => CK_OUT <= CK_IN(1); when "10" => CK_OUT <= CK_IN(2); when others => CK_OUT <= CK_IN(3); end case; end process CMUX; end architecture

    FPGA, VHDL & Co. ·JK · ·8 Antworten

  • Thread

    CPLD-Problem: moving average

    SIG_OUT_DATA <= SIG_ADC1_DATA; end if; WHEN "0100" => --REFRESH MEAN --xxxx SIG_OUT_DATA <= SIG_ADC_MEAN; WHEN OTHERS => SIG_OUT_DATA <= SIG_OUT_DATA; END CASE;

    Takt Latency eingeführt. Das ginge aber auch so: [vhdl] akku <= akku - akku/32 + in_data when rising_edge(clk); out_data <= akku/32 when rising_edge(clk); [/vhdl] Oder konservativer so: [vhdl] process begin wait until rising_edge(clk); akku <= akku

    FPGA, VHDL & Co. ·S. K. · ·34 Antworten

  • Thread

    Verständnisprobleme synchron, asynchron

    definiert hast, speziell bei onehot-Codierung (such mal danach). Deshalb sollte man ein case-Zweig "when others => new_state <= irgendein_state; -- z.B. fehlerstate" vorsehen.

    definiert hast, speziell bei onehot-Codierung (such mal danach). Deshalb sollte man ein case-Zweig "when others => new_state <= irgendein_state; -- z.B. fehlerstate" vorsehen. -> Ja, hilft aber z.B. auch nix, wenn man durch ein asynchrones Signal in einen gültigen State (der aber trotzdem falsch ist

    FPGA, VHDL & Co. ·Martin · ·61 Antworten

  • Thread

    Glixon to Bcd wandler

    architecture Behavioral of Glixon2BCD is begin process (glixon) begin case glixon is when "0000" => bcd <= "0000"; when "0001" => bcd <= "0001"; when "0011" => bcd <= "0010"; when "0010" => bcd <= "0011"; when "0110" => bcd <= "0100"; when "0111" => bcd <= "0101"; when "0101" => bcd <= "0110"; when "0100" => bcd <= "0111"; when "1100" => bcd <= "1000"; when "1000" => bcd <= "1001"; when others => bcd <= "0000"; end case; end process

    FPGA, VHDL & Co. ·GAL · ·1 Antworten

  • Datei

    uart_tx.vhd

    STD_LOGIC; -- Reset. rst : IN STD_LOGIC; -- 'High' if transmitter shall start to send tx_byte. -- 'Low' when nothing should be send. tx_ack : IN STD_LOGIC; -- Data byte to be send. tx_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- 'High' if transmitting process has started. -- 'Low' when system is in idle mode

    in „UART Kommandos funktionieren nicht“ · FPGA, VHDL & Co. ·

  • PDF

    54600-Series_Datasheet__5968-8152EN_.pdf

    , 8, 16, 32, 64 … to 16383 High Resolution Mode 54621A/D, 54622A/D, 54624A: 12 bits of resolution when ≥500 µs/div, (average mode with ave = 1) 54641A/D, 54642A/D: 12 bits of resolution when ≥100 µs/div, (average mode with ave = 1) Filter Sinx/x interpolation (single shot BW = sample rate/4 or bandwidth

    in „suche Oszillograf HP54642D“ · Markt ·

  • Thread

    Vivado-Post-Synthesis Simulation liefert falsche Werte

    process(CLK) begin if rising_edge(CLK)THEN case state_LED is When CNT1 => if SUM>2000000 then state_LED<=SETLEDS; else SUM <= SUM+1; end if; When SETLEDS => SUM<=0; LEDACTIVE<= not LEDACTIVE; state_LED<=CNT1; When others => state_LED<=CNT1; end case; end if; end process; LEDS<=LEDACTIVE; end Behavioral; [/vhdl]

    FPGA, VHDL & Co. ·Empa · ·25 Antworten

  • Thread

    Statemachine hängt sich weg

    3) Ich setzte den Debugvector meist ausserhalb der state machiene. Also: debugvector = "00001" when state_sig = STATE1 else "00010" when state_sig = STATE2 else ..... "10000" when state_sig = STATE_LAST; Abtakten vor Ausgabe nicht vergessen: process(clk) Begin if rising_edge(clk) then if reset = '1' then debug_output_pins <= (others => '0'); else debug_output_pins <= debugvector; end if; end if; end process; Dann läuft der debugausgang zwar einen Takt nach, aber er belügt dich nicht. schau dir den vhdlcode

    FPGA, VHDL & Co. ·Daniel · ·19 Antworten

  • Thread

    Can't determine definition of operator ""and"" -- found 0 possible definitions

    begin if state = "100" then if inc'event and inc = '0' then case op(2 downto 0) is when "001" => res := a + b; when "010" => res := a - b; when "100" => res := (aV(7 downto 0) and bV(7 downto 0)); when others => res :=0; end case; end if; end if; end process; end behavioral; Auch when "100" => res := aV and bV; geht nicht. Die noetigen Libs sind doch eigentlich eingebunden? Auch kompiliert der Code, wenn ich die "and"-Zeile auskommentiere und das Programm arbeitet auf der Hardware

    FPGA, VHDL & Co. ·Eric Cartman · ·7 Antworten

  • PDF

    vhdl.pdf

    "0110" => LED := "0111111"; when "0111" => LED := "1100010"; when "1000" => LED := "1111111"; when "1001" => LED := "1110111"; when others => LED := "-------"; don’t care: std_logic_1164 end case; case SEL is 4-fach Multiplexer when "00" => O <= A; when "01" => O <= B; when "10" => O <= C; when others => O <= D; end case; 32 5.1 Anweisungen Loop Modellierung verschiedener Schleifen. Neben der Vereinfachung von Ausdrucken,¨ lassen sich so auch Wiederholungen

    in „VHDL Einführung“ · FPGA, VHDL & Co. ·

  • Datei

    VHDL_Code_Gustl__2.txt

    downto 0) ); end SOURCE; architecture Behavioral of SOURCE is signal COUNT : unsigned(9 downto 0):=(others => '0'); signal SCHALTER_GRENZE : unsigned(9 downto 0):=(others => '0'); --wie mach ich das SCHALTER_GRENZE den Wert von Schalter Eingang übernimmt ? begin -- Vieleicht so ? SCHALTER_GRENZE <= SCHALTER

    in „VHDL Code Aufgabe, HILFE! :/“ · FPGA, VHDL & Co. ·

  • Datei

    SOURCE.vhd

    downto 0) ); end SOURCE; architecture Behavioral of SOURCE is signal COUNT : unsigned(9 downto 0):=(others => '0'); signal Schalter_grenze : unsigned(9 downto 0):=(others => '0'); begin Schalter_grenze <= unsigned(SCHALTER(9 downto 0)); -- Hier hab ich es umgewandelt process (CLK) begin if rising_edge(CLK

    in „VHDL Code Aufgabe, HILFE! :/“ · FPGA, VHDL & Co. ·

  • Thread

    Schieberegister und Latch

    falsch. Gemeint war aber wohl [vhdl] constant C_SREG_RSTVAL : std_logic_vector(15 downto 0) := (others => '1); [/vhdl]

    signal ncssr : std_logic_vector(2 downto 0) := "000"; begin ncssr <= ncssr(1 downto 0) & ncs when rising_edge(clk); -- ncs auf Mastertakt einsynchronisieren sreg <= sreg(14 downto 0) & sin when rising_edge(sclk); -- mit lokalem sclk einschieben par_out <= sreg when ncssr(

    FPGA, VHDL & Co. ·Karl · ·15 Antworten

  • Datei

    lpout.diff

    @ --- "*" and "+" differs only in bit 0 so this bit can be ignored - case lpbits(6 downto 1) is - when "010101" => store <= '1'; - when others => store <= '0'; + case lpbits is + when "0101011" => store <= '1'; setbusy <= '1'; + when "0101010" => store <= '1'; setbusy <= '0'; + when others => store <

    in „Einfaches CPLD-Beispiel für Xilinx?“ · FPGA, VHDL & Co. ·

  • Datei

    fsm_01.vhd

    process Z_SPEICHER; FSM: process --(CLK_FSM,State) begin wait until rising_edge(CLK_FSM); case State is when z0 => sAc_reg <=(others=>'0'); sBs_reg <=(others=>'0'); senSPI <= '0'; senCordic <= '0'; when z1 => senSPI <= '1'; senCordic <= '0'; when z2 => senSPI <= '0'; senCordic <= '1'; sAc_reg <= (Spi_c - haelfte); sBs_reg <= (Spi_s - haelfte); end case; end process FSM; Cos_Cor <= signed(sAc_reg);-- when senCordic = '1'; Sin_Cor <= signed(sBs_reg);-- when senCordic = '1'; EnSpi <= senSpi; EnCor <= senCordic; end fsm_01;

    in „FSM mit ADC synchronisieren“ · FPGA, VHDL & Co. ·

  • Datei

    multiply.vhd

    mb_next <= mb; result_next <= result; count_next <= count; -- default done <= '0'; case state is when IDLE => if edge = '1' then next_state <= ADD; count_next <= 2; ma_next <= unsigned( multiplicand); mb_next <= resize( unsigned( multiplier), mb'length); result_next <= ( others => '0'); end if; when

    in „Sequential System Design Using ASM Charts“ · FPGA, VHDL & Co. ·

  • Datei

    dma.vhdl

    busy signal io_busy : std_logic; -- Shadows: signal s_addr_src : unsigned(ADDR_W-1 downto 0) := (others => '0'); signal s_addr_dst : unsigned(ADDR_W-1 downto 0) := (others => '0'); signal count : unsigned(16-1 downto 0); type dma_state_t is ( S_IDLE, S_START, S_RUNNING, S_DONE ); signal state : dma_state_t

    in „Wie größeres FPGA Projekt aufbauen“ · FPGA, VHDL & Co. ·

  • PDF

    vhdl.pdf

    "0110" => LED := "0111111"; when "0111" => LED := "1100010"; when "1000" => LED := "1111111"; when "1001" => LED := "1110111"; when others => LED := "-------"; don’t care: std_logic_1164 end case; case SEL is 4-fach Multiplexer when "00" => O <= A; when "01" => O <= B; when "10" => O <= C; when others => O <= D; end case; 32 5.1 Anweisungen Loop Modellierung verschiedener Schleifen. Neben der Vereinfachung von Ausdrucken,¨ lassen sich so auch Wiederholungen

    in „Projekte für die Schule“ · Offtopic ·

  • Thread

    Fehler bei Case-Anweisung

    ... process(clk) begin if rising_edge(clk) then case data_in(wert1 downto wert1 -3) is when "0000" => data_out <= '1'; when "0010" => data_out <= '1'; when "1011" => data_out <= '0'; when others => data_out <= '0'; end case; [/pre] Dies ist nur ein Beispielcode, da der

    FPGA, VHDL & Co. ·Daniel R. · ·6 Antworten

  • Datei

    time_ms.vhd

    std_logic_vector(1 downto 0) ) return std_logic_vector is variable ms_outp : std_logic_vector(3 downto 0) := (others => '0'); variable ms_outp_lcd : std_logic_vector(8 downto 0) := (others => '0'); begin ms_outp_lcd(7 downto 4) := x"3"; case sel_par is when "00" => ms_outp := time_16bit mod 10; when "01" => ms_outp := (time_16bit / 10) mod 10; when "10" => ms_outp := (time_16bit / 100) mod 10; when "11" => ms_outp := (time_16bit / 1000); end case; ms_outp_lcd(3 downto 0) := ms_outp; return ms_outp_lcd; end to_time_ms; end time_ms;

    in „VHDL function für Umwandlung eines 16Bit Wertes??“ · FPGA, VHDL & Co. ·

  • Datei

    VHDL_Code_Gustl.txt

    downto 0) ); end SOURCE; architecture Behavioral of SOURCE is signal COUNT : unsigned(9 downto 0):=(others => '0'); signal COUNT_SCHALTER : unsigned(3 downto 0):=(others => '0'); --Schalter Zaehler nur 4 Bit weil mehr braucht ich derzeit ned weil 13 signal SCHALTER_GRENZE : unsigned(3 downto 0):="1101";

    in „VHDL Code Aufgabe, HILFE! :/“ · FPGA, VHDL & Co. ·