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PIC16F1939.pdf
Period Register, Prescaler and Postscaler • Two Capture, Compare, PWM Modules (CCP): - 16-bit Capture, max. resolution 125 ns - 16-bit Compare, max. resolution 125 ns - 10-bit PWM, max. frequency 31.25 kHz • Three Enhanced Capture, Compare, PWM modules (ECCP): - 3 PWM time-base options - Auto-shutdown and
in „MPLAB delay und xtalfreq richtig benutzen“ · Mikrocontroller und Digitale Elektronik ·
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Reference_Manual.pdf
. . 210 5.3.10 Auto-wakeup from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . 211 5.4 PWR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 5.4.1 Power control register 1 (PWR_CR1) . . . . . . . . . . . . . . . . . . . . . . . .
in „STM32G474RE UART“ · Mikrocontroller und Digitale Elektronik ·
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_ATSAMD20E18A-MU.pdf
time Tstart from a clock request until the clock is available for the peripheral is between: Tstart_max= Clock source startup time + 2 × clock source periods + 2 × divided clock source periods Tstart_min Clock source startup time + 1 × clock source period + 1 × divided clock source period The time between
in „Exposed Pad anschließen? (ATSAMD20E18A-MU und ELMOS E981.03)“ · Mikrocontroller und Digitale Elektronik ·
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Module_SS2013_-_WS2013-14.pdf
zur Codierung von Bild- und Videosignalen. Dazu z hlen das Design von Quantisierern am Beispiel der Max-Lloyd Optimalquantisierung, die Entropiecodierung mit den Beispielen Hu▯man-Codierung und arithmetischer Codierung sowie Lau ngencodierung.Dar ber hinaus wird auf die Grundlagen der Vektorquantisierung
in „Spezialisierung im Studium? Oder eher generalistisch?“ · Ausbildung, Studium & Beruf ·
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PIC18f6622.pdf
17-3: (T4CON). FOSC logFPWM- 5. Configure the CCPx module for PWM operation. PWM Resolution (max) = ---------bits log(2) Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared. TABLE 17-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency
in „PIC 18F6622 Zeit um EEPROM zu schreiben“ · Mikrocontroller und Digitale Elektronik ·
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PIC_18F8722_Data_Sheet.pdf
17-3: (T4CON). ⎛FOSC ⎞ log⎝FPWM-⎠ 5. Configure the CCPx module for PWM operation. PWM Resolution (max) = ---------bits log(2) Note: If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared. TABLE 17-3: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz PWM Frequency
in „PIC 18F6527 mit 32MHz Takten“ · Mikrocontroller und Digitale Elektronik ·
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R32C-152_Users_Manual.pdf
...................................................................................................211 15.1.3 One-shot Timer Mode........................................................................................................... 215 15.1.4 Pulse-width Modulation Mode..........................
in „Keine UART Programmierung bei R32C möglich“ · Mikrocontroller und Digitale Elektronik ·
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UM10398_-_LPC11xx_UserManual.pdf
in this document is subject© NXP B.V. 2011. All rights reserved. User manual Rev. 4 — 4 March 2011 211 of 414 NXP Semiconductors UM10398 Chapter 13: LPC111x/LPC11Cxx C_CAN controller Table 191. CAN message interface command mask registers (CANIF1_CMDMSK, address 0x4005 0024 and CANIF2_CMDMSK, address
in „Cortex-M UART im Polling-Betrieb“ · Mikrocontroller und Digitale Elektronik ·
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rudi_____RX-V4A_TSR-400.pdf
displayed. displayed. Day (0D to 9999D) T2-1 T1-4 T1-7 MAIN VOL:----- T1-2. POWER-RELAY ON OUTLVL MAX: 00 RST NUM: 00003 Maximum value / The operation frequency of the power relay (RY541) Minimum value / 0 to FF −80.0 to +16.0 dB is displayed. T1-8. PROTECTION LOCK T1-5. POWER OFFTIME-OUT The operation
in „Test in der Schaltung STR3A400“ · Analoge Elektronik und Schaltungstechnik ·
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8052AH-BASIC_Users_Manual.pdf
163 LJMP 30H 164 2115 44495350165 D_MSG: DB "DISPLAY IS A COMMAND, NOT A STATEMENT" 2119 4C415920 211D 49532041 2121 20434F4D 2125 4D414E44 2129 2C204E4F 212D 54204120 2131 53544154 2135 454D454E 2139 5422 166 213B 594F5520167 C_MSG: DB "YOU NEED A COMMA TO MAKE DISPLAY WORK" 213F 4E454544 2143 20412043
in „Was ist das für eine Platine“ · Mikrocontroller und Digitale Elektronik ·
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en.DM00091010.pdf
. . . . . . . . . . . 564 Table 79. Examples of TIMEOUTA settings for various I2CCLK frequencies (max tTIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 Table 80. Examples of TIMEOUTB settings for various I2CCLK frequencies . . .
in „EFM32F030 und Standby“ · Mikrocontroller und Digitale Elektronik ·
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xc2200_um_v2.1_2008_08_vol2per.pdf
Input Signal Limits System Clock = 10 MHz Input GPT1 Input System Clock = 40 MHz Frequ. Divider Phase Max. Input Min. Level Factor BPS1 Duration Max. Input Min. Level Frequency Hold Time Frequency Hold Time 1.25 MHz 400 ns GPT/8 01 B 4 × GPT 5.0 MHz 100 ns 625.0 kHz 800 ns GPT/16 00 B 8 × GPT 2.5 MHz 200
in „Schlechte Datenblätter von Infineon (CAN)“ · Mikrocontroller und Digitale Elektronik ·
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stm32l431_reference_manual.pdf
. . . . . . . . . . 1001 Table 148. Examples of TIMEOUTA settings for various I2CCLK frequencies (max t TIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002 Table 149. Examples of TIMEOUTB settings for various I2CCLK frequencies . .
in „ADC differential mode“ · Mikrocontroller und Digitale Elektronik ·
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stm32l431_reference_manual.pdf
. . . . . . . . . . 1001 Table 148. Examples of TIMEOUTA settings for various I2CCLK frequencies (max t TIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002 Table 149. Examples of TIMEOUTB settings for various I2CCLK frequencies . .
in „Offset Data alignment“ · Mikrocontroller und Digitale Elektronik ·
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stm32l431_reference_manual.pdf
. . . . . . . . . . 1001 Table 148. Examples of TIMEOUTA settings for various I2CCLK frequencies (max t TIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1002 Table 149. Examples of TIMEOUTB settings for various I2CCLK frequencies . .
in „DMA one shot mode“ · Mikrocontroller und Digitale Elektronik ·
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Datei
version_1p3_assembler.lst
96: ;***************************************************************************** 97: ; 98: ; The max. value for XTAL is now 78627473 Hz, for use BASIC-52 with 99: ; Dallas 80C320 high speed / low power microcontroller (33 MHz). ASEM-51 V1.3 Copyright (c) 2002 by W.W. Heinz PAGE 3 Line I Addr Code Source
in „Basic für 80C31“ · Mikrocontroller und Digitale Elektronik ·
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rm0444-stm32g0x1-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
. . . . . . . . . . . 966 Table 173. Examples of TIMEOUTA settings for various I2CCLK frequencies (max t TIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 967 Table 174. Examples of TIMEOUTB settings for various I2CCLK frequencies . .
in „Problem mit Clock Configuration beim STM32G031“ · Mikrocontroller und Digitale Elektronik ·
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MC9S08DZ60.pdf
MCGOUT BUSCLK ÷ 2 MCGLCLK XOSC CPU BDC ADC MSCAN FLASH EEPROM ADC has min and Flash and EXTAL XTAL max frequency EEPROM have requirements.See frequency * The fixed frequency clock (FFCLK) is internally theADCchapterand requirements for synchronizedtothebusclockandmustnotexceedonehalf of the bus clock
in „Delay Funktion für Freescale“ · Mikrocontroller und Digitale Elektronik ·
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PIC18F46J11_39932D.pdf
hardware integrity checking and • Tunable Internal Oscillator (31 kHz to 8 MHz, ±0.15% Typical, ±1% Max). safety interlocks prevent unintentional • 4x PLL Option configuration changes • Hardware Real-Time Clock and Calendar (RTCC): • Secondary Oscillator using Timer1 @ 32 kHz • Fail-Safe Clock Monitor
in „PIC18F46J11 und RTC. Quarz nötig? Anfängerfrage Übersicht verloren ;-(“ · Mikrocontroller und Digitale Elektronik ·
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H83003H.PDF
Features (cont) Feature Description Operating modes Four MCU operating modes Address Address Initial Bus Max. Bus Mode Space Pins Width Width Mode 1 1 Mbyte A to A 8 bits 16 bits 0 19 Mode 2 1 Mbyte A 0to A19 16 bits 16 bits Mode 3 16 Mbyte A 0to A23 8 bits 16 bits Mode 4 16 Mbyte A 0to A23 16 bits 16 bits
in „H8/300 Frage (genauer H8/3003)“ · Mikrocontroller und Digitale Elektronik ·
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R8C22-23_Group_Hardware_Manual.pdf
clock Period of CPU clock Following total (flash memory time is the time operates) × 12 cycles + 30µs (max.) × 6 cycles × 20 cycles from wait mode until an interrupt 1 Period of system clock (flash memory × 12 cycles Same as above Same as above routine is stops) executed. T1 T2 T3 Flash memory activation
in „Fragen zu Renesas µC (R5F2122CKFP)“ · Mikrocontroller und Digitale Elektronik ·
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panasonic_tx-50dx800e_tx-50dxw804_chassis_la67.pdf
HDAVI Control 5” function. DIGITAL AUDIO OUT PCM / Dolby digital, Fibre optic USB 1/2/3 USB1 :DC 5V, Max 900mA [SuperSpeed USB (USB 3.0)] USB2/3 :DC 5V, Max 500mA [Hi-Speed USB (USB 2.0)] ETHERNET RJ45, IEEE802.3 10BASE-T / 100BASE-TX CARD SLOT Common interface slot (Complies with CI+) x 2 Wireless LAN
in „Schaltregler SMD Marking“ · Analoge Elektronik und Schaltungstechnik ·
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TMS470.pdf
by adding 844 to PC. ; bit[1] of PC is forced to zero. ; Note that the 16-BIS opcode will ; contain 211 as the Word8 value. 16-Bit Instruction Set 5-19 Format 7: load/store with register offset 5.7 Format 7: load/store with register offset Figure 5-8. Format 7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1
in „Vergleiche mit (2^n)-1 und -(2^n) schneller?“ · Mikrocontroller und Digitale Elektronik ·
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ps42p3sx_ch._d58a.pdf
CONPENSA 616 PC TTX Contrast offset 00 BLUE CONPENSA 616 -------------------------------------- NR SCALE MAX 64 WTE GAIN 58 R GAIN 127 127 NR SCALE MIN 18 RAST VSIZE 1023 G GAIN 127 127 DE GAIN COR 03 RAST HSIZE 895 B GAIN 127 127 DE GAIN CLIP (90/90/60) SHARP OFFSET 17 R,CR OFFSET 54 63 CE UPPER 240 CLK DLY
in „Netzteil prüfen wie stelle ich das richtig an?“ · Analoge Elektronik und Schaltungstechnik ·
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rej09b0101_16c29hm_2_.pdf
2007 page 36 of 458 REJ09B0101-0112 M16C/29 Group 5. Resets VCC ROC td(P-R) More than td(ROC) RESET Max. 2 ms CPU clock: 28 cycles CPU clock FFFFC16 Content of reset vector Address FFFFE16 Figure 5.2 Reset Sequence ____________ Table 5.1 Pin Status When RESET Pin Level is “L” Pin name Status P0 to P3,
in „Zeitproblem bei Softwarepwm“ · Mikrocontroller und Digitale Elektronik ·
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Exp_Meth_In_RF_Des--Wes_Hayward.pdf
filter transfer functions showing attenuation. passband ripples of 1,2, and 3 dB. also know as the max flat delay filter, is These extreme ripple values are rarely often used as a starting point for bandpass used, but illustrate the concepts. Note filters with minimum ringing. This will be that there
in „Literatur zum Selbstbau von Sendern und Empfängern“ · HF, Funk und Felder ·
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avrdude_out.txt
Size #Pages MinW MaxW ReadBack ----------- ---- ----- ----- ---- ------ ------ ---- ------ ----- ----- --------- hfuse 0 0 0 0 no 1 0 0 9000 9000 0x00 0x00 Block Poll Page Polled Memory Type Mode Delay Size Indx Paged Size
in „avrdude braucht lange zum Beenden (Linux)“ · Compiler & IDEs ·
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slau144i.pdf
Mode Bits OSCOFF, CPUOFF, and GIE are not affected. SLAU144I–December 2004–Revised January 2012 CPUX 211 Submit Documentation Feedback Copyright © 2004–2012, Texas Instruments Incorporated Instruction Set Description www.ti.com 4.6.2.45 SETZ * SETZ Set zero bit Syntax SETZ Operation 1 → N Emulation BIS
in „Anfängerprogramm TimerA MSP430“ · Mikrocontroller und Digitale Elektronik ·
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64F3048F16-Hitachi.pdf
input-only pins Operating modes Seven MCU operating modes Mode Address Space Address Pins Initial Bus Width Max. Bus Width Mode 1 1 Mbyte A19to A0 8 bits 16 bits Mode 2 1 Mbyte A to A 16 bits 16 bits 19 0 Mode 3 16 Mbytes A23to A0 8 bits 16 bits Mode 4 16 Mbytes A to A 16 bits 16 bits 23 0 Mode 5 1 Mbyte A19to
in „CPU Melkanlage auslesbar? 64F3059F16“ · Mikrocontroller und Digitale Elektronik ·
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siplace-s27hm.pdf
a maximum height of 6 mm and, with the 6-segment collect&place head (S-27 HM), on components to a max. of 8.5 mm. The transport height can be set to allow the machines to be integrated into lines with 830, 900, 930 or 950 mm transport height. Communication between the PCB conveyors of the individual
in „Siplace 80 Potentialverteiler“ · Mikrocontroller und Digitale Elektronik ·
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Datei
report_all.txt
| SSTL2_I | | 2.50 | PAD212 | H3 | None L | fpga_0_DDR_SDRAM_DDR_Addr | O | SSTL2_I | | 2.50 | PAD211 | H2 | None L | fpga_0_DDR_SDRAM_DDR_Addr | O | SSTL2_I | | 2.50 | PAD210 | H1 | None L | fpga_0_DDR_SDRAM_DDR_Clk_ | O | DIFF_SSTL2_I | | 2.50 | PAD208 | J5 | None L | fpga_0_DDR_SDRAM_DDR_Clk_ | O
in „Place and Route partially locked IO bus“ · FPGA, VHDL & Co. ·
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PIC32MX3XX_Data_Sheet.pdf
the CRC. Bits > PLEN will 0’ on any read. © 2008 Microchip Technology Inc. Preliminary DS61143E-page 211 PIC32MX3XX/4XX (1) REGISTER 10-6: DCRCXOR: DMA CRC XOR ENABLE REGISTER r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 31 bit 24 r-x r-x r-x r-x r-x r-x r-x r-x — — — — — — — — bit 23 bit 16 R/W
in „PIC32 und Assembler“ · Mikrocontroller und Digitale Elektronik ·
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MC9S08MM128RM.pdf
Divider Settings Bus PRDIV8 DIV fFCLK Program/Erase Timing Pulse (Binary) (Decimal) (5 s Min, 6.7s Max) 20 MHz 1 12 192.3 kHz 5.2 s 10 MHz 0 49 200 kHz 5 s 8 MHz 0 39 200 kHz 5 s 4 MHz 0 19 200 kHz 5 s 2 MHz 0 9 200 kHz 5 s 1 MHz 0 4 200 kHz 5 s 200 kHz 0 0 200 kHz 5 s 150 kHz 0 0 150 kHz 6.7
in „Freescale s08mm128 und USB“ · Mikrocontroller und Digitale Elektronik ·