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Datei
picoboot.vhd
data input write => '0' -- 0=write 1=read ); com_code_process: process (vsel) begin case vsel is when "111" => com_code <= x"0B"; -- Fast Read when "101" => com_code <= x"03"; -- Read when "110" => com_code <= x"E8"; -- Read Array when others => com_code <= x"E8"; -- Read Array end case; end process
in „FPGA-bitfile in SPI Seriell Flash programmieren“ · FPGA, VHDL & Co. ·
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Datei
lcd.vhd
(62 downto 56) ; segment_enable <= "1011" ; when others => pixels <= segment_shiftreg(69 downto 63) ; segment_enable <= "0111" ; end case ; end if; end process; process(clk) begin if rising_edge(clk) then if btn_rst = '1' then --Enable Signal für
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Datei
Create_Bit_Stream.VHD
elsif(CLK'event and CLK = '1')then if(GATE = '1' and S_ONE_TIME = '0')then case S_RESET_CONFIG is when "01" => S_RESET <= '1'; when "10" => S_RESET <= '0'; when others => NULL; end case; end if; end if; end process; -- ****** Wandlerwerte in Speicher_A schreiben ****** process (CLR,CLK,RESET_ADC_A,S_REGB
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Datei
TEM_uni_5_adc_stream.vhd
ADC_data_ready <= AD7356_56_data_ready; when others => ADC_data <= fifo_counter; ADC_data_ready <= fifo_counter_ready; end case; --------- write to FIFO ------------------------------------ fifo_wr <= '0'; if fsm_fifo = fifo_wait then if ADC_data_ready
in „Wie Clockdomain crossing für FT232H, wie debuggen?“ · FPGA, VHDL & Co. ·
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Datei
user_logic.vhd
, slv_reg1, slv_reg2, slv_reg3 ) is begin case slv_reg_read_sel is when "1000" => slv_ip2bus_data <= slv_reg0; when "0100" => slv_ip2bus_data <= slv_reg1; when "0010" => slv_ip2bus_data <= slv_reg2; when "0001" => slv_ip2bus_data <= slv_reg3; when others => slv_ip2bus_data
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Datei
txt_util.vhd
= 'U'; when 31 => c := 'V'; when 32 => c := 'W'; when 33 => c := 'X'; when 34 => c := 'Y'; when 35 => c := 'Z'; when others => c := '?'; end case; return c; end chr; -- convert integer to string using specified
in „Rechnen im Hex-Dezimalsystem mit Dezimalanzeige“ · FPGA, VHDL & Co. ·
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Datei
i2s_shifter_2x_slave.vhdl
variable bitcnt : integer range 0 to 15; begin if res = '1' then -- reset all buffers in_1_buffer <= (others => '0'); in_2_buffer <= (others => '0'); in_3_buffer <= (others => '0'); in_4_buffer <= (others => '0'); out_1_buffer <= (others => '0'); out_2_buffer <= (others => '0'); out_3_buffer <= (others =>
in „I2S nach"TheMason" in Betrieb nehmen“ · FPGA, VHDL & Co. ·
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Datei
adc_logic.vhd
0'; WR_2_EN <= '1' WHEN (RD_CNT = "01" AND RD = '0') ELSE '0'; WR_3_EN <= '1' WHEN (RD_CNT = "10" AND RD = '0') ELSE '0'; D <= X_DATA(7 DOWNTO 0) WHEN WR_1_EN = '1' ELSE (OTHERS => 'Z'); D <= Y_DATA(7 DOWNTO 0) WHEN WR_2_EN = '1' ELSE (OTHERS => 'Z'); D <= X_DATA(11 DOWNTO 8) & Y_DATA(11 DOWNTO 8) WHEN WR_3_EN = '1' ELSE (OTHERS => 'Z'); END Behavioral;
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Datei
HyperBus.vhd
Burst_length: std_logic:='0'; --0: 2Bytes, 1:64Bytes signal Burst_counter_100: unsigned(7 downto 0):=(others => '1'); signal RX_Data_Counter: integer range 0 to 127:=0; signal RX_Data: std_logic_vector(15 downto 0):=(others => '0'); signal TX_Data: std_logic_vector(15 downto 0):=(others => '0'); signal DQ_OUT
in „HyperBus Ideen“ · FPGA, VHDL & Co. ·
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Datei
tb_division.vhd
end if; if cycles mod 3 = 0 then divisor_tvalid_nxt := '0'; else divisor_tvalid_nxt := '1'; end if; when others => -- Test will stop imminently - do nothing null; end case; -- Drive handshake signals with local variable values s_axis_dividend_tvalid <= dividend_tvalid_nxt; s_axis_divisor_tvalid <= divisor_tvalid_nxt; -- Drive AXI slave channel A payload -- Drive 'X's on payload signals when not valid if dividend_tvalid_nxt /= '1' then s_axis_dividend_tdata <= (others => 'X'); else -- TDATA: This holds the dividend operand. It is 24 bits wide and byte-aligned with the operand in the LSBs
in „Simulation des Divider Generator 3.0“ · FPGA, VHDL & Co. ·
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Datei
anz5.vhd
mux_arch of mux is --signal zwmux: STD_LOGIC_VECTOR (3 downto 0); begin mux1 <= reg(15 downto 12) when auson="1000" else reg(11 downto 8) when auson="0100" else reg(7 downto 4) when auson="0010" else reg(3 downto 0); --others zwmux <= "1111"; end mux_arch; --Onehotcounter entity onehot is generic (v1
in „Fehlermeldung bei Synthese (Ausgabe 7 Segment)“ · FPGA, VHDL & Co. ·
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Datei
adc_board.vhd
RESET => '0' ); -- debugging "lights" led <= addr_adc(7 downto 0); with state select point <= "0001" when IDLE, --1 "0010" when SRREAD, --2 "0100" when SRWRITE, --3 "0000" when others; --0 spp_data <= "10101010"; spp_busy <= '1'; -- clock adc_clock_o <= clk; -- dac config range_sel <= '1'; -- sram config
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Datei
arctanFP.vhd
BEGIN IF rising_edge(clk) THEN IF nrst = '0' THEN stateatan <= 0; ce1 <= '0'; nd <= '0'; InpA <= (OTHERS => '0'); InpB <= (OTHERS => '0'); atanFPo <= (OTHERS => '0'); --TestOutp <= (OTHERS => '0'); --(OTHERS => '0'); ELSE CASE stateatan IS WHEN 0 => IF ceatan = '1' THEN InpA <= Xinp; InpB <= Yinp; ce1
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Datei
i3c2.vhd
"1101" => delay <= x"2000"; when "1110" => delay <= x"4000"; when others => delay <= x"8000"; end case; when OPCODE_I2C_STOP => bitcount <= unsigned(clk_divide); state <= STATE_I2C_STOP; when OPCODE_NOP => pcnext <= pcnext+1; when others => error <= '1'; end case; end if; when others => state <= STATE_RUN; pcnext <= (others => '0'); skip <= '1'; end case; end if; end process; end Behavioral;
in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·
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Datei
code.vhd
bitisset : STD_LOGIC_VECTOR(255 downto 0); begin index := 0; bitisset := BITISSETxC; STATExDN <= (others => (others => '0')); CExC <= (others => '0'); BITISSETCExC <= '0'; BITISSETIxC <= (others => '0'); --insert statements to decode internal output signals --below is simple example if state = st3_proc
in „Komischer Fehler: ERROR:HDLCompiler:463 - "../Huffman.vhd" Line 170“ · FPGA, VHDL & Co. ·
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Datei
nibble_data.vhd
when x"8A3" => counter <= (others => '0'); busy <= '0'; --flag_full2 <= '0'; -- -- MIT LOOP EINFÜGEN der Daten!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! -- when others => --data <= "0000"; -- if counter
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Datei
vga_controller.vhd
-------- -- horizontal and vertical counters signal hcounter : std_logic_vector(10 downto 0) := (others => '0'); signal vcounter : std_logic_vector(10 downto 0) := (others => '0'); -- active when inside visible screen area. signal video_enable: std_logic; begin -- output horizontal and vertical counters
in „VGA Controller VHDL Speicheranbindung“ · FPGA, VHDL & Co. ·
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Datei
pseuzufgen.vhd
<= 6; when "0110" => NUMBER_OF_REGS <= 7; when "0111" => NUMBER_OF_REGS <= 8; when "1000" => NUMBER_OF_REGS <= 9; when "1001" => NUMBER_OF_REGS <= 10; when "1010" => NUMBER_OF_REGS <= 11; when "1011" => NUMBER_OF_REGS <= 12; when "1100" => NUMBER_OF_REGS <= 13; when "1101" => NUMBER_OF_REGS <= 14; when others => NUMBER_OF_REGS <= 15; end case; end process NUMB_REGISTERS; P1: process(CLK, RESET) begin if RESET = '0' then -- low
in „flexibler Pseudozufallszahlengenerator! was mache ich falsch?“ · FPGA, VHDL & Co. ·
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Datei
mt48lc16m16a2.vhd
Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00"; SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0'); SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0'); BEGIN -- CS# Decode WITH Cs_n SELECT Cas_in <= TO_BIT (Cas_n, '1') WHEN '0', '1' WHEN '1', '1' WHEN OTHERS; WITH Cs_n SELECT Ras_in <= TO_BIT (Ras_n, '1') WHEN '0', '1' WHEN '1', '1' WHEN OTHERS; WITH Cs_n SELECT We_in <= TO_BIT (We_n, '1') WHEN '0', '1' WHEN '1', '1' WHEN OTHERS; -- Commands Decode Active_enable <= NOT(Ras_in) AND Cas_in AND We_in; Aref_enable
in „Problem mit vital.timing und vital.primitives“ · FPGA, VHDL & Co. ·
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Datei
ALU.vhd
begin if rising_edge(CLK) then if RST = '1' then COut <= '0'; Z <= '0'; E <= '0'; H <= '0'; Y <= (OTHERS => '0'); elsif CE ='1' then if Oa = Ob then E <= '1'; else E <= '0'; end if; if Oa > Ob then H <= '1'; else H <= '0'; end if; case Sel is when "0000" => Y <= YB; when "0001" => Y <= YAdd(31 downto
in „Problem mit "Eigenbau" Pipeline ALU“ · FPGA, VHDL & Co. ·
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Datei
adc_board.vhd
"100000000000" then adc_clock <= NOT adc_clock; adc_latency_cntr <= "000000000000"; end if; when "11" => if adc_latency_cntr = "111111111111" then adc_clock <= NOT adc_clock; adc_latency_cntr <= "000000000000"; end if; when others => adc_clock <= clk; end case; end if; end process; ------------
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Datei
Lauflicht1.vhd
downto 8); when "10" => -- disp 3 sseg_anode_data <= "1011"; sseg_data <= xy_data(7 downto 4); when "11" => -- disp 4 sseg_anode_data <= "0111"; sseg_data <= xy_data(3 downto 0); when others => sseg_data <= "1111";
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Datei
code.txt
"; when "0000001111" => res := "1000111"; when others => res := "1111111"; -- nur fuer Simulation end case; return res; end; -- bei groesseren Designs wuerde man die Funktion in ein Package auslagern ------
in „LED-Multiplex aufm dem Spartan-3 von Digilent“ · FPGA, VHDL & Co. ·
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Datei
max1000_01_test.vhd
--LED <= Z_DATA(15 downto 8) when USER_BTN = '0' else Z_DATA(7 downto 0); SEN_SDI <= SEN_SDI_buffer3; SEN_SPC <= SEN_SPC_buffer; SEN_SPC_buffer <= SPC_R when state_read = '1' else SPC_WR; SPC_R <= SPI_read_counter(1) when SPI_read_counter
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Datei
gcpu_soc.vhd
: in std_logic_vector(3 downto 0) := (others => '0'); rs_index : in std_logic_vector(3 downto 0) := (others => '0'); rd : out std_logic_vector(15 downto 0) := (others => '0'); rs : out std_logic_vector(15 downto 0) := (others => '0'); rin : in
in „ModelSim Problem 'X' anstatt '1' in std_logic_vector signal“ · FPGA, VHDL & Co. ·
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Datei
BWS_2011_TFT.vhd
= '0' when Reset = '0' else DB(1) when (ADR(7 downto 0) = x"11" and IORQ = '0' and WR = '0') else IO11_Latch ; -- Takteingang auf intern VDCLK legen.. VDCLK <= Takt_In ; -- 20Mhz Eingangstakt = VDCLK -- Takterzeugung
in „ISE erzeugt immerwieder andere JED Datei“ · FPGA, VHDL & Co. ·
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PDF
PMOLED_2.4_WHITE_P19706-A01_3PF0MIM9J.pdf
contains confidential and propNeither it nor the information contained herein shall be disclosed to others or duplicated or used for others without the express written consent of RiTdisplay. http://www.ritdisplay.com REVISION RECORD REV. REVISION DESCRIPTION REV. DATE REMARK X01 INITIAL RELEASE 2012. 11
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Datei
Uhr.vhd
(0) <= (others => '0'); if minuten_neu(1) < 5 then minuten_neu(1) <= minuten_neu(1) + 1; else minuten_neu(1) <= (others => '0'); if stunden_neu(0) < 3 then stunden_neu(0) <= stunden_neu(0) + 1; else stunden_neu(0) <= (others => '0'); if stunden_neu(1) < 2 then stunden_neu(1) <= stunden_neu(1) + 1; else stunden_neu(1) <= (others => '0'); end if; -- if stunden_neu(1) end if; -- if stunden_neu(0) end if; -- if minuten_neu
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Datei
master2master.vhd
if Reset = '1' then RX_reg <= (others => '0'); vSCL_M0 := 'U'; vSCL_M1 := 'U'; elsif SYSCLK = '1' and SYSCLK'event then case RX_state is when RX_IDLE => RX_reg <= (others => '0'); when RX_M0toSLA => if SCL_M0 = '1' and vSCL_M0 = '0' then
in „Master zu Master Kommunikation SPI“ · FPGA, VHDL & Co. ·
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Datei
mt46v16m16.vhd
(OTHERS => '0'); -- Row address mux CASE Bank_addr IS WHEN "00" => Rows_addr := B0_row_addr; WHEN "01" => Rows_addr := B1_row_addr; WHEN "10" => Rows_addr := B2_row_addr; WHEN OTHERS => Rows_addr := B3_row_addr
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Datei
BWS_TFT.vhd
fertig Videodaten ausschieben -- Idee INVERS Modus 10H/11H evl gleich hier mit rein Zei_INV <= '1' when D35_36 = x"11" -- InversModus ein else '0' when D35_36 = x"10" or QD41_42 = 69 ; -- InversModus aus -- INVERS-Auswertung BWS_Inv <= IO11_Latch when Zei_INV ='0' -- Umschaltung INVERS else not IO11_Latch
in „Codecheck Erstlingswerk VHDL Newbie :)“ · FPGA, VHDL & Co. ·
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Datei
simple_osc.vhd
is when "00" => null; -- wait when "01" => case wave_form is --- wellenform berechnen -- saw when "00" => wave_out <= osc_count (15 downto 8); -- sqr when "01" => if osc_count (15) = '1' then wave_out <= (others
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Datei
Quicksort.vhd
clock_quicksort) variable temp : data_type_ram; begin if rising_edge (clock_quicksort) then case state is when init_state => read_address_quicksort_internal <= (others => '0'); write_address_quicksort_internal <= (others => '0'); state <= idle_state; when idle_state => if write_enable_quicksort = '1' then state
in „must be a globally static expression“ · FPGA, VHDL & Co. ·
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Datei
7seg.txt.txt
when 9 => SEG_10 <= "11001110"; TEMP <= TEMP - 90; when others => SEG_10 <= "00000000"; end case; case TEMP is -- 1er Stelle when 0 => SEG_1 <= "01111110"; when 1 => SEG_1 <= "00001100"; when 2 => SEG_1
in „8-bit Binärcode auf 7-Segmentanzeige anzeigen“ · FPGA, VHDL & Co. ·
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Datei
ALU.vhd
: process (reset, A_reg, B_reg, ACC_reg, u_instruction, Databus, internal_bus) begin ALU_Out <= (others => '0'); ACC_Temp <= ALU_out; A_tmp <= Databus; B_tmp <= Databus; Flags_tmp <= "0001"; out_enable <= '0'; Index_tmp <= ACC_reg; CASE u_instruction is when op_lda => A_tmp <= databus; when op_ldb =>
in „Problem: Latches oder unkorrektes Verhalten“ · FPGA, VHDL & Co. ·
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Datei
MemoryController.vhd
if initDone = false then case initState is when 0 => ramAddress <= "00010000111010100011100"; ramCRE <= '1'; ramADV <= '0'; ramCE <= '0'; ramOE <= '0'; ramWE <= '0'; ramLB <= '0'; ramUB <= '0'; tristateWE <= '0'; initState <= initState + 1; when 1 => ramADV <= '1'; ramWE <= '1'; initState <= initState + 1; when 2 => initState <= initState + 1; when 3 => initState <= initState + 1; when 4 => ramCE <= '1'; initState <= initState + 1; when 5 => ramAddress <= (others => '0'); ramCRE <= '0'; ramADV <= '0'; ramCE
in „Xilinx (Digilent Nexys4) mit Micron SRAM Ansteuerung“ · FPGA, VHDL & Co. ·
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Datei
watch.vhd
<= "0010010"; --Zahl 5 when 6 => min0 <= "0000010"; --Zahl 6 when 7 => min0 <= "1111000"; --Zahl 7 when 8 => min0 <= "0000000"; --Zahl 8 when 9 => min0 <= "0010000"; --Zahl 9 when others => min0 <= "1111111"; end case; --FÃŒr
in „Digital Clock“ · FPGA, VHDL & Co. ·
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Datei
Incremental_Encoder.vhd
when "1111" => up_down <= '0'; ce <= '0'; error <= '0'; -- keine Bewegung when others => null; end case; end process; -- Counter process (ce, RESET) -- reagiert auf CLK und RESET begin if (RESET = '1') then -- bei RESET t_cnt <= (others => '1'); -- clear (others => '0') setzt alle Ausgaben auf '0' t_cnt(23) <= '0'; -- t_cnt2 <= (others => '0'); -- clear (others => '0') setzt alle Ausgaben auf '0' elsif (rising_edge(ce)) then -- bei
in „maximale Xilinx CPLD clock Frequenz“ · FPGA, VHDL & Co. ·
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Datei
RS232.vhd
? SioTXState <= IDLE; -- j: fertig end if; when others => SioTXState <= IDLE; end case; end if; end process; TX <= TX_Register(0); ReceiveSM: process (RESET, CLK) begin if (RESET='1') then SioRXState <= IDLE; RX_Register <= (others=>'1'); elsif (rising_edge(CLK)) then RX_DataReady <= '0'; case SioRXState is when IDLE => RX_Counter <= BIT_Reload/2; RX_Register <= (others=>'1'); if (RX_Entprellt = '0') then -- Startbit erkannt SioRXState <= RECEIVE; end if; when RECEIVE => RX_Counter <= RX_Counter - 1; if (RX_Counter
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Datei
lcd_driver.vhd
when SET_LINE_MSB => LCD_DATA <= "1000"; -- Line 1: 1000 / Line 2: 1100 LCD_E <= '1'; NEXT_STATE <= SET_LINE_MSB_WAIT; when SET_LINE_MSB_WAIT => NEXT_STATE <= SET_LINE_LSB; when SET_LINE_LSB => LCD_DATA
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Datei
picoboot.vhd
bit data input WRITE => '0' -- 0=write 1=read ); ComCode_process: process (Vsel) begin case Vsel is when "111" => ComCode <= X"0B"; -- Fast Read when "101" => ComCode <= X"03"; -- Read when "110" => ComCode <= X"E8"; -- Read Array when others => ComCode <= X"E8"; -- Read Array end case; end process; p_fsm
in „Spartan 3A über FTDI USB IC flashen“ · FPGA, VHDL & Co. ·
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Datei
Lauflicht1.vhd
downto 8); when "10" => -- disp 3 sseg_anode_data <= "1011"; sseg_data <= xy_data(7 downto 4); when "11" => -- disp 4 sseg_anode_data <= "0111"; sseg_data <= xy_data(3 downto 0); when others => sseg_data <= "1111";
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Datei
npl30d.vhd
Expansion port ------------------------------------------------------------------------------- CAR <= A when CS4 = '1' else (others=>'Z'); NCRD <= NOE when CS4 = '1' else 'Z'; NCWR <= NWE when CS4 = '1' else 'Z'; CDR <= D when ((CS4 = '1') and (NWE = '0')) else (others=>'Z'); D <= do_reg when ((P26 = '0') and (NOE = '0')) else CDR when ((CS4 = '1') and (NOE = '0')) else (others=>'Z'); ------------------------------------------------------------------------------- --- Handle NPL External Enable Register ----------------------------
in „Probleme bei der Umstellung von Verilog nach VHDL“ · FPGA, VHDL & Co. ·
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Datei
npl30d.vhd
Expansion port ------------------------------------------------------------------------------- CAR <= A when CS4 = '1' else (others=>'Z'); NCRD <= NOE when CS4 = '1' else 'Z'; NCWR <= NWE when CS4 = '1' else 'Z'; CDR <= D when ((CS4 = '1') and (NWE = '0')) else (others=>'Z'); D <= do_reg when ((P26 = '0') and (NOE = '0')) else CDR when ((CS4 = '1') and (NOE = '0')) else (others=>'Z'); ------------------------------------------------------------------------------- --- Handle NPL External Enable Register ----------------------------
in „Probleme bei der Umstellung von Verilog nach VHDL“ · FPGA, VHDL & Co. ·
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Datei
meanvalue.vhdl
clk); state <= next_state; end process; Averaging : process (state, v_in_new) begin case state is when reset => counter <= (others => '0'); summe_u <= (others => '0'); next_state <= idle; when idle => v_out_new <= '0'; --nothing to do, just stay and wait when inc => counter <= counter + 1; next_state <= add; when add => summe_u <= summe_u + unsigned(v_in); if(counter = 3) then counter <= (others => '0'); next_state <= mean; else next_state <= idle; end if; when mean => v_out <= std_logic_vector(summe_u(13 downto
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Datei
gh_fifo_sync_sr.vhd
-- Write address counter ------------- ----------------------------------------- add_WR_CE <= '0' when (ifull = '1') else '0' when (WR = '0') else '1'; process (clk,rst) begin if (rst = '1') then add_WR <= (others => '0'); elsif (rising_edge(clk)) then if (srst = '1') then add_WR <= (others => '0');
in „gh_fifo_sync_sr: loadless signals?“ · FPGA, VHDL & Co. ·
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Datei
TSBUF_V2.vhd
WRITE_ENABLE; RD_TSBUF <= not RD and WR; READ_BUS: IN_DATA <= INOUT_DATA; INOUT_DATA <= X_DATA(7 downto 0) when WRITE_1_ENABLE = '1' else (others => 'Z'); INOUT_DATA <= ("0000" & X_DATA(11 downto 8)) when WRITE_2_ENABLE = '1' else (others => 'Z'); INOUT_DATA <= Y_DATA(7 downto 0) when WRITE_3_ENABLE = '1' else (others => 'Z'); INOUT_DATA <= ("0000" & Y_DATA(11 downto 8)) when WRITE_4_ENABLE = '1' else (others => 'Z'); SET_CFG_REG: process(RD_TSBUF, IN_DATA) begin if RD_TSBUF = '1' then CFG_DATA(7 downto 6) <= IN_DATA
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Datei
VHDL.txt
- when "1010" => led <= x"cf"; -- --XX---- when "1011" => led <= x"9f"; -- -XX----- when others => led <= x"ff"; -- -------- end case; end if; -- S1 Schleife -- Taster abfragen if (key(1)='1') then led <=
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Datei
crtc.vhd
< mode(4)) else '0'; vga_r <= pixel(15 downto 11) when visible = '1' else (others => '0'); vga_g <= pixel(10 downto 5) when visible = '1' else (others => '0'); vga_b <= pixel( 4 downto 0) when visible = '1' else (others => '0'); -- fifo state fifo_full <= '1' when fifo_rp = fifo_wp + 1 else '0'; fifo_almost <= '1' when fifo_rp = fifo_wp + 2 else '0'; fifo_empty <= '1' when fifo_rp = fifo_wp else '0'; -- request and handle pixel data px_first <= '1' when fifo_hcount
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Datei
merge_data.vhd
data change end if; end process; -- states process (w_state_reg,i_tick) begin case w_state_reg is when idle => -- when regular state is "idle" o_done <= '0'; w_index_next <= (others => '0'); if(i_tick ='1') then w_state_next <= start; end if; when start => -- when regular state is "start" o_busy <= '1'; w_data_next <= (others => 'Z'); if(g_o_wordwith <= g_i_wordwith) then w_state_next <= short; else w_state_next <= long; end if; when short => -- when regular state is "short" if i_tick = '0' then w_data_next( ((g_o_wordwith
in „Serielles zusammenfassen von Bitvektoren einer UART (8 Bit -> 20 Bit ect.)“ · FPGA, VHDL & Co. ·