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LED_Display_driver_chip_SSD1306_DataSheet.pdf
NC -940 356 51 FR -151.955 -352.83 131 SEG5 2774.5 356 211 SEG84 -988.5 356 52 CL -89.815 -352.83 132 SEG6 2727.5 356 212 SEG85 -1035.5 356 53 VSS -25.665 -352.83 133 SEG7 2680.5 356 213 SEG86 -1082.5 356 54 CS# 38.635 -352.83 134 SEG8 2633.5 356 214 SEG87 -1129.5 356 55 RES# 109.835 -352.83 135 SEG9
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PDF
LED_Display_driver_chip_SSD1306_DataSheet.pdf
NC -940 356 51 FR -151.955 -352.83 131 SEG5 2774.5 356 211 SEG84 -988.5 356 52 CL -89.815 -352.83 132 SEG6 2727.5 356 212 SEG85 -1035.5 356 53 VSS -25.665 -352.83 133 SEG7 2680.5 356 213 SEG86 -1082.5 356 54 CS# 38.635 -352.83 134 SEG8 2633.5 356 214 SEG87 -1129.5 356 55 RES# 109.835 -352.83 135 SEG9
in „SSD1306/1309 Library zum Darstellen von Text auf OLED Displays“ · Projekte & Code ·
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PDF
SSD1306.pdf
NC -940 356 51 FR -151.955 -352.83 131 SEG5 2774.5 356 211 SEG84 -988.5 356 52 CL -89.815 -352.83 132 SEG6 2727.5 356 212 SEG85 -1035.5 356 53 VSS -25.665 -352.83 133 SEG7 2680.5 356 213 SEG86 -1082.5 356 54 CS# 38.635 -352.83 134 SEG8 2633.5 356 214 SEG87 -1129.5 356 55 RES# 109.835 -352.83 135 SEG9
in „SH1106 Init-Sequenz“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Solomon_Systech_LED_Display_driver_chip_SSD1306.pdf
NC -940 356 51 FR -151.955 -352.83 131 SEG5 2774.5 356 211 SEG84 -988.5 356 52 CL -89.815 -352.83 132 SEG6 2727.5 356 212 SEG85 -1035.5 356 53 VSS -25.665 -352.83 133 SEG7 2680.5 356 213 SEG86 -1082.5 356 54 CS# 38.635 -352.83 134 SEG8 2633.5 356 214 SEG87 -1129.5 356 55 RES# 109.835 -352.83 135 SEG9
in „Mit Wire.h über I2C auf LCD-Display 1602 zugreifen“ · Mikrocontroller und Digitale Elektronik ·
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ssd1309.pdf
417 290 VCOMH -2770.02 -337.5 51 D0 30 -399 131 VCC 2418.75 417 211 SEG79 -581.25 417 52 D1 90 -399 132 SEG0 2381.25 417 212 SEG80 -618.75 417 53 D2 150 -399 133 SEG1 2343.75 417 213 SEG81 -656.25 417 54 D3 210 -399 134 SEG2 2306.25 417 214 SEG82 -693.75 417 55 VSS 270 -399 135 SEG3 2268.75 417 215 SEG83
in „Display EA OLED L128-6“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Solomon_Systech_LED_Display_driver_chip_SSD1306.pdf
NC -940 356 51 FR -151.955 -352.83 131 SEG5 2774.5 356 211 SEG84 -988.5 356 52 CL -89.815 -352.83 132 SEG6 2727.5 356 212 SEG85 -1035.5 356 53 VSS -25.665 -352.83 133 SEG7 2680.5 356 213 SEG86 -1082.5 356 54 CS# 38.635 -352.83 134 SEG8 2633.5 356 214 SEG87 -1129.5 356 55 RES# 109.835 -352.83 135 SEG9
in „SSD1306/1309 Library zum Darstellen von Text auf OLED Displays“ · Projekte & Code ·
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Datei
bootload.lst
SecondBootStart 85 # define BOOTSTART SecondBootStart 86 # endif 87 ;---------------------------- max possible buffer size ----------------- 88 89 .equ BufferSize,((SRAM_SIZE / 2) - PAGESIZE) 90 .macro testpage 91 .if BootStart % BufferSize 92 .set BufferSize, BufferSize - PAGESIZE 93 .if BootStart
in „Peter Danneggers Bootloader (fastboot) für AVR-GCC-Toolchain“ · Projekte & Code ·
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Datei
usbdrv.c
FEATURE_COMPATBLE_ID 'W','I','N','U','S','B',0,0, //Compatible ID String 0,0,0,0,0,0,0,0, //Sub-compatible ID String 132,0, 4,0, // MS_OS_20_FEATURE_REG_PROPERTY 7,0, // Multiple NULL-terminated Unicode strings (REG_MULTI_SZ) // unicode "DeviceInterfaceGUIDs" 0x2A,0, 'D',0,'e',0,'v',0,'i',0,'c',0,'e',0, 'I',0,'n',0,'t
in „uC für 0,20€ CH552 / CH554 von WCH Billig Micro mit USB Funktion, Chip vorstellung“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Dokumentation.PDF
P312P2 P1 X4 PAT503 A02 Y0A04PPAR2422 PAIC1044R2302 PAR12010X9 X3P9P2857A6P2P24XP200PAC2501PAIC150COC132 PAIC109 PAIC1040R2340PATPAT10 PAT102 C9 A172 PAC3025PAPAIC1PAIC15012 1COY1A03PAIC1013 PAIC1036PAICPAIC1PAIC14010 PA1CA43002C9 COC37PAC301 PAPAIC1PAIC150111L1L2PAC3PAIC10COC45AIPAIC1PAICPAIC1PAIC1407
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S29JL064H_00_A7_e.pdf
block erase 2 ms N 22h 44h 0000h Typical timeout for full chip erase 2 = not supported) 23h 46h 0005h Max. timeout for byte/word write 2s typical 24h 48h 0000h Max. timeout for buffer write 2 times typical 25h 4Ah 0004h Max. timeout per individual block erase 2 typical N 26h 4Ch 0000h Max. timeout for full
in „[Verkaufe] 5xSDRAM (4Meg x 16 x 4 Banks) und 5xFLASH (64Meg 8 o. 16 Bit)“ · Markt ·
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Datei
PCM_master.vhd
is generic (clock_frequency: integer:= 49152000; -- Hz : here enter main clock frequency LRCK_CNT_MAX: integer:= 64; -- LRCK_CNT_MAX represents the divider max value referring to LRCK_CNT for generation of LRCK as urgently needed by PCM5142 --spi_clock_frequency: integer:= 3125000; -- Hertz : here enter spi clock frequency length_bits : integer := 16; DIN_CNT_MAX: integer:= 64 -- for generation of -2^32-1 value (test purposes) ); port ( -- this device's ports CLK : in std_logic; -- main clock the same as SCK for PCM5142 BCK_OUT : out std_logic; LRCK_OUT : out
in „DDS mit DE0-Nano Board nur niedrige Frequenzen?“ · FPGA, VHDL & Co. ·
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83c185.pdf
Non-AN Gen Power Down 22 17 5 0.66 0.200 4 1 100BASE-TX Operation 100BASE-TX /w traffic 261 66 20 132 40 63 19 Idle 245 50 15 132 40 63 19 Energy Detect Power Down 45 17 5 24 7 4 1 AN General Power Down 45 17 5 24 7 4 1 Non-AN Gen Power Down 22 17 5 0.66 0.200 4 1 Notes: 1. Each LED indicator in use
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PDF
83c185.pdf
Non-AN Gen Power Down 22 17 5 0.66 0.200 4 1 100BASE-TX Operation 100BASE-TX /w traffic 261 66 20 132 40 63 19 Idle 245 50 15 132 40 63 19 Energy Detect Power Down 45 17 5 24 7 4 1 AN General Power Down 45 17 5 24 7 4 1 Non-AN Gen Power Down 22 17 5 0.66 0.200 4 1 Notes: 1. Each LED indicator in use
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PDF
W25Q256JW_SPI_RevJ_03102021_Plus.pdf
: 0.45mm. Ball Opening: 0.35mm PCB ball land suggested <= 0.35mm Millimeters Inches Symbol Min Nom Max Min Nom Max A --- --- 1.20 --- --- 0.047 A1 0.26 0.31 0.36 0.010 0.012 0.014 A2 --- 0.85 --- --- 0.033 --- b 0.35 0.40 0.45 0.014 0.016 0.018 D 7.90 8.00 8.10 0.311 0.315 0.319 D1 4.00 BSC 0.157 BSC
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PDF
Datenblatt_Xilinx_Virtex-5_LX.pdf
10 137.5 000011010 00 650 000010111 10 143.75 000011011 00 675 000001100 01 150 000011100 00 700 (Max) Table 14 - Synthesizer Clock Outputs for M and N Values The following table shows the Virtex-5 pin connections for the two differential clock outputs of the synthesizer. Net Name I/O Type Virtex-5
in „Ethernetschnittstelle programmieren - Anfänger“ · FPGA, VHDL & Co. ·
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PDF
Datenblatt_Xilinx_Virtex-5_LX.pdf
10 137.5 000011010 00 650 000010111 10 143.75 000011011 00 675 000001100 01 150 000011100 00 700 (Max) Table 14 - Synthesizer Clock Outputs for M and N Values The following table shows the Virtex-5 pin connections for the two differential clock outputs of the synthesizer. Net Name I/O Type Virtex-5
in „Ethernetschnittstelle Xilinx Virtex 5“ · FPGA, VHDL & Co. ·
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PDF
magnetic.pdf
which has two extreme values along the hysteresis curve Bx,1− B x,2 B x,1− B x,2 µmin = min , and µ max = max . (5.58) H x,1Hx,2H x,1− H x,2 Hx,1,Hx,2H x,1− H x,2 Hereµ min andµ max aretheminimumandmaximumslopeofthehysteresischaracteristics. The inequality µmin ≤ µ ≤ µ max (5.59) is obvious, from which
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Datei
DDS.vhd
in integer:=0; DOUT : out std_logic_vector (31 downto 0); DIN_CNT_MAX: in integer:=0 ); end DDS; -------------------------------------------------- Architecture BEHAVIOUR of DDS is -------------------------------------------------- signal RESULT : signed (31 downto 0)
in „DDS mit DE0-Nano Board nur niedrige Frequenzen?“ · FPGA, VHDL & Co. ·
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PDF
MFprot_LP.PDF
DESCRIPTION Pin Name DIP No. I/O Type Buffer Type Description LED1 1 O TTL Red LED connection. 25ma max sink current LED2 2 O TTL Green LED connection. 25ma max sink current RESET 3 I ST Reset pin internally pulled high. Active low. Normally not connected BEEP 4 O TTL BEEP output pin (active LOW), 25ma
in „Spannung/Strom glätten für RFID-Leser“ · Mikrocontroller und Digitale Elektronik ·
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PDF
SAK-C167CR-LM_HA.pdf
mode to a multiplexed bus mode. The following PORT1 pins also serve for alternate functions: P1H.4 132 I CC24IO CAPCOM2: CC24 Capture Input P1H.5 133 I CC25IO CAPCOM2: CC25 Capture Input P1H.6 134 I CC26IO CAPCOM2: CC26 Capture Input P1H.7 135 I CC27IO CAPCOM2: CC27 Capture Input XTAL2 137 O XTAL2: Output
in „Problem mit Infinion C167CR mit AM29F200B-70SE“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Resources_an5457-rf-matching-network-design-guide-for-stm32wl-series-stmicroelectronics.pdf
the line. It can also be expressed as a function of the reflection coefficient ratio, as follows. VZ max 1 + Γ VSWR = VZ min = 1 − Γ, 1 ≤ VSWR ≤ ∞ If VSWR = 1.0, there is no reflected power. The return loss (RL) is a function of the reflection coefficient but expressed in dB. P RL = 10 × log10 incident
in „STM32WLE5CCU6 LoRa-Antennenendesign review“ · HF, Funk und Felder ·
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PDF
AN5457.pdf
the line. It can also be expressed as a function of the reflection coefficient ratio, as follows. VZ max 1 + Γ VSWR = VZ min = 1 − Γ, 1 ≤ VSWR ≤ ∞ If VSWR = 1.0, there is no reflected power. The return loss (RL) is a function of the reflection coefficient but expressed in dB. P RL = 10 × log10 incident
in „868MHz Impedanzmatching - Fragen zum Matching-vorgehen“ · HF, Funk und Felder ·
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PDF
TMC2209_datasheet_rev1.07.pdf
and DIR interface timing AC-Characteristics clock period is tCLK Parameter Symbol Conditions Min Typ Max Unit step frequency (at maximum f ½ f STEP CLK microstep resolution) fullstep frequency f f /512 FS CLK STEP input minimum low time tSL max(FILTSD 100 ns tCLK0) STEP input minimum high time tSH max(
in „Industrielle [3D-Drucker] Bastelgrundlagen“ · Mechanik, Gehäuse, Werkzeug ·
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FR_Family_MB91F109.pdf
12.00 15.00 (.472) (.591) REF NOM Details of "A" part 0.15(.006) INDEX 100 26 0.15(.006) 0.15(.006)MAX LEAD No. 1 25 "B" 0.40(.016)MAX "A" 0.50(.0197)TYP 0.18 –0.03 0.127 –0.02 +.003 0.08(.003) M +.002 Details of "B" part .007 –.001 .005 –.001 0.10±0.10 (.004±.004) (STAND OFF) 0.10(.004) 0.50±0.20(.020
in „Fujitsu MB91F011 internal flash read/write“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Energizer_AAA_AA_AlkaliMangan_ohne.pdf
:45 1,39 131 04:22:00 1,39 131 04:22:15 1,39 131 04:22:31 1,39 131 04:22:46 1,39 131 04:23:01 1,39 132 04:23:17 1,39 132 04:23:32 1,39 132 04:23:47 1,39 132 04:24:02 1,39 132 04:24:18 1,39 132 04:24:33 1,39 132 04:24:48 1,39 132 04:25:03 1,39 133 04:25:19 1,39 133 04:25:34 1,39 133 04:25:49 1,39 133
in „Varta Super Heavy Duty ver**ung“ · Mechanik, Gehäuse, Werkzeug ·
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ATmega32.pdf
to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 33
in „STK500 als ISP“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATM16_doc2466.pdf
to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 33
in „ISP - Pinbelegung“ · Mikrocontroller und Digitale Elektronik ·
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Datei
display_t.cpp
1]) { PBuf = SIGNAL_MAX[channel-1]; SIGNAL_MAX[channel-1] = SIGNAL_MIN[channel-1]; SIGNAL_MIN[channel-1] = PBuf; } #ifdef _Debug_QM_ //printf("channel: %d SIGNAL_MAX[channel-1] %d, SIGNAL_MIN[channel-1] %d, ixs %d, ixss %d
in „Wittig(welec) DSO W20xxA Open Source Firmware (Teil4)“ · Mikrocontroller und Digitale Elektronik ·
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tiny13.pdf
BOTTOM. There are two cases that give a transition without Compare Match. OCR0A changes its value from MAX, like in Figure 32. When the OCR0A value is MAX the OCn pin value is the same as the result of a down-counting Compare Match. To ensure symmetry around BOTTOM the OCn value at MAX must correspond to
in „ATtiny13 Datenblatt External Clock Source on T0-Pin“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Ateme16.pdf
to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 33
in „Atmega16 und spi bus“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Ateme16.pdf
to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 33
in „Atmega16 und spi bus“ · Mikrocontroller und Digitale Elektronik ·
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PDF
MFRC530-NXP.pdf
solution 5. Quick reference data Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit T amb ambient temperature 40 - +150 C T stg storage temperature 40 - +150 C V digital supply voltage 0.5 +5 +6 V DDD V DDA analog supply voltage 0.5 +5 +6 V V DD(TVDD) TVDD supply voltage
in „[V] 3St. RFID (Mifare) Lese ICs NXP MFRC530 SO32 (4€)“ · Markt ·
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PDF
PIC18Fxx2.pdf
that can be configured as: In-Circuit Debug (ICD) via two pins - Capture input: capture is 16-bit, max. resolution 6.25 ns (CY /16) CMOS Technology: - Compare is 16-bit, max. resolution 100 nsCY) Low power, high speed FLASH/EEPROM - PWM output: PWM resolution is 1- to 10-bit, technology max. PWM freq
in „AD1 und AD2 Multiplexen (PIC18F452)“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Infineon_TLE9263QX.pdf
Voltage Regulator 2 V CC2, max -0.3 – 28 V VCC2= 40V for P_4.1.4 Load Dump, max. 400 ms; Voltage Regulator 3 V CC3REF,max-0.3 – 28 V VCC3REF= 40V for P_4.1.5 (VCC3REF) Load Dump, max. 400 ms; Voltage Regulator 3 (VCC3B)V -0.3 – V V V = 40V for P_4.1.25 CC3B,max S CC3B + 10 Load Dump, max. 400 ms; Voltage Regulator 3 V CC3SH,max VS – VS V – P_4.1.26 (VCC3SH) - 0.30 + 0.30 Wake Inputs WK1..3 V -0.3 – 40 V – P_4.1.6 WK, max Fail Pin FO1 V FO1, max -0.3 – 40 V
in „SBC für CAN/LIN bei einem 24V Bordnetz“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Acer_Aspire_5742G_Compal_LA-5893P_Rev0.1_Schematic.pdf
PC105 N F F V VGA@ PC106 0_0402_5% C .1U_0402_16V7K 470P_0603_50V8J C 2 6 7 9 1 3 2 1 3 2 1 2 1 VGA@ PR132 10_0402_5% 2 1 +NVVDD_SENSE +NVVDD_SENSE 23 1 7 J 4 1 1 Layout Note: 1 1 8 1 1 2 1 Close IC Rds=4.5mΩ(typ) C 0 VGA@ PR133 R 4 P _ 7 33K_0402_1% P _ @ PC998 單單單單單單 Pin15 5.6mΩ(max) VGA@ PR135 @ 0 2 5
in „Laptop Akkus ausbauen und mit Netzteil betreiben“ · PC Hard- und Software ·
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PDF
Mega32.pdf
to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 33
in „AVR Timer/Counter Zeit berechnen“ · Mikrocontroller und Digitale Elektronik ·
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PDF
lg_flatron_l1800p_lb886f_ch_cl-29.pdf
Depth : 237 mm (9.33'') SOG (Sync On Green) Height : 428 mm (16.85'') -Min Digital 508 mm (19.99'') -Max 3-2. Video Input Signal 1) Type : R, G, B Analog 7. WEIGHT (with SPEAKER) 2) Voltage Level : 0~0.71 V Net. Weight : 8.8kg (19.40 lbs) a) Color 0, 0 : 0 Vp-p Gross Weight : 11.3kg (24.91 lbs) b) Color
in „Überspannung in Mehrparteien-Wohunung. Baustrom, oder Kabel angebohrt?“ · Haus & Smart Home ·
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PDF
datasheet.pdf
Register Baud Rate Timer 1 f SMOD Mode 12-clock mode 6-clock mode OSC C/T Mode Reload Value Mode 0 Max 1.67 MHz 3.34 MHz 20 MHz X X X X Mode 2 Max 625 k 1250 k 20 MHz 1 X X X Mode 1, 3 Max 104.2 k 208.4 k 20 MHz 1 0 2 FFH Mode 1, 3 19.2 k 38.4 k 11.059 MHz 1 0 2 FDH 9.6 k 19.2 k 11.059 MHz 0 0 2 FDH
in „Info zum SAB80C382 gesucht!“ · Mikrocontroller und Digitale Elektronik ·
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PDF
GPS-Compendium_Book__GPS-X-02007_.pdf
.94 Figure 88: 24-hour HDOP values, in area with with no shadow/obstruction of satellite visibility (max. HDOP < 1.9).......................................95 Figure 89: 24-hour HDOP values, in area with with strong shadow/obstruction of satellite visibility (max. HDOP > 20)............................
in „Verschlüsselte Militär(?)daten innerhalb des GPS-Signals“ · HF, Funk und Felder ·
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PDF
APT_Communications_Protocol.pdf
35 Data Part No/Axis Serial Number Counts per Unit 36 37 38 39 40 41 42 43 44 45 46 47 Data MinPos Max Pos Max Accn 48 49 50 51 52 53 54 55 56 57 58 59 Data Max Dec Max Vel Reserved Reserved 60 61 62 63 64 65 66 67 68 69 70 71 Data Reserved Reserved Reserved Reserved 72 73 74 75 76 77 78 79 Data Reserved
in „Thorlabs Laser-Source mit über FTDI232BM ansteuern“ · Mikrocontroller und Digitale Elektronik ·
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PDF
LDS517_Displaycontroller.pdf
Row 262k-Color / 56 Icons OLED Controller & Driver Version 1.2 Document No: LTT517DS-05 Prepared By: Max Son E-Mail: max_son@leadis.com REVISION HISTORY Date Page Contents Version 3 Changed : VCC Æ VDC / VDR 4 Inserted : VROW Generator Block in the Block Diagram 5 Changed : VCC Æ VDC, VDR pin description
in „Verkaufe OLED Displays FullColor 128*128 bzw. 96*64“ · Markt ·
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PDF
ml50x_schematics.pdf
Debug PWR Page 25-26 D Mictor, Trace Jack SofTouch Diff SMA Clocks Page 9 Page 11 Switcher 5.0V@10A max Optional GPIO Linear USER Clock 0.9V@1.4A max Page 10 Page 9 Switcher 3.3V@10A max Glock DVI Generator Linear Codec Page 15 2.5V@3A max Page 9 Conn Page 16 2.5V@3A maxCAUX Linear Flash Video In Page 20 Codec Page 17 Linear MGT PLL 1.2V@3A max Virtex 5 C LXT / SXT / FXT C Linear - MGT AVTT RX ZBT SRAM AC97 1.2V@3A max Page 2-6 Audio Page 20 Page 18 Switcher 1.8V@10A max Platform FLASH IIC Linear - MGT AVCC EEPROM 1.0V@3.0A max Page 8 Page
in „DDR2 RAM Ansteuerung mit Virtex-5 ML507“ · FPGA, VHDL & Co. ·
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PDF
Part_1_Physical_Layer_Specification_Ver3.01_Final_100218.pdf
xb R [76:76] device size C_SIZE 12 n xxxh R [73:62] max. read current @VDD min VDD_R_CURR_MIN 3 xxxb R [61:59] max. read current @VDD max VDD_R_CURR_MAX o3 xxxb R [58:56] max. write current @VDD maxVDD_W_CURR_MAX c 3 xxxb R [52:50] device size multiplier
in „MicroSD STM32 und Mosfet“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ATmega8.pdf
contains timing data for basic Timer/Counter operation. The figure shows the count sequence close to the MAX value. 70 ATmega8(L) 2486Z–AVR–02/11 ATmega8(L) Figure 28. Timer/Counter Timing Diagram, No Prescaling clkI/O clkTn (clI/O1) TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1 TOVn Figure 29 shows the same timing
in „Mikrocontroller und 15'' TFT LCD“ · Mikrocontroller und Digitale Elektronik ·
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PDF
db_atmega8.pdf
to eight bits. In phase correct PWM mode the counter is incremented until the counter value matches MAX. When the counter reaches MAX, it changes the count direction. The TCNT2 value will be equal to MAX for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 51
in „ADC-Input und Auswahlverfahren“ · Mikrocontroller und Digitale Elektronik ·
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PDF
I-BOTT.PDF
Table 4–1 Value DS1990A – DS1996 DS1982–DS1986 DS1920 Vpull–up min 2.8V V IHmin 2.2V V ILx 0.8V 1 VOL max 0.4V at 4 mA t min 60 s SLOT tSLOT max 120 s RDV 15 s Special Power Supply None VPP Programming Pulse 1 mA at 5V NOTES: 1. Also see Figure 4–5 for worst caseOL min at 50⋅C for DS1990A, DS1982, DS1991
in „Design eines hotplugfähigen I2C-Bussystems und Auswahl des Steckverbinders“ · Mikrocontroller und Digitale Elektronik ·
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PDF
NT7533Lcd.pdf
(H=1). Caution As the programming range for the internally generated VLCD allows values above the max. allowed VLCD, the customer has to ensure while setting the VOP register and selecting the temperature compensation (TC), that under all conditions and including all tolerances the VLCD remains below
in „Seriell (4-Wire)-LCD-Ansteuerung mit NT7533“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Book_of_Knowledge_german.pdf
Minimale Eingangsspannung 2 V I,NOM IOUTMI O2 I V V Maximale Eingangsspannung 3 V I,NOM OU TMAX O3 IN,MAX 4 V I V IN,IN OUT,NOM O4 IOUT,NOM Nennausgangsstrom 5 V I V IN,IN OUTMI O5 Minimaler Ausgangsstrom 6 V I V IOUT,MIN IN,IN OU TMAX O6 7 V I V I Maximaler Ausgangsstrom I,MAX OUT,NOM O7 OUT,MAX 8 V I
in „Eingangsfilter DC-DC-Wandler - mal wieder“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
RECOM_de_Buch.pdf
Minimale Eingangsspannung 2 V I,NOM IOUTMI O2 I V V Maximale Eingangsspannung 3 V I,NOM OU TMAX O3 IN,MAX 4 V I V IN,IN OUT,NOM O4 IOUT,NOM Nennausgangsstrom 5 V I V IN,IN OUTMI O5 Minimaler Ausgangsstrom 6 V I V IOUT,MIN IN,IN OU TMAX O6 7 V I V I Maximaler Ausgangsstrom I,MAX OUT,NOM O7 OUT,MAX 8 V I
in „Schaltnetzteil Grundlage“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
uploaded_files_documents_org13xx_series_datasheet_u2841.pdf
ratings only. Stresses exceeding Absolute Maximum Ratings may damage the device. Parameter Symbol Min Max Units Power Supply Voltage VCC 0 5.5 V UART Input Voltage V -0.5 7 V RX UART Output Source/Sink Current ITX -10 +10 mA SPI/GPIO Input Voltage VIO_IN 0 1.98 V SPI/GPIO Output Source/Sink Current IIO_OUT
in „Inbetriebnahme ORG-1315“ · Mikrocontroller und Digitale Elektronik ·