-
Datei
FT2232H_minimal_A.vhd
FT2232H------------------------------------------------- signal counter: unsigned(8 downto 0):=(others => '0'); signal new_burst: std_logic:='0'; signal fifo_miss: unsigned(3 downto 0):=(others => '0'); type fsm_fifo_type is(fifo_reset, fifo_check, fifo_write, fifo_wait); signal fsm_fifo: fsm_fifo_type
-
Datei
Reg_bidirectional.vhd
WRITE READ=0 WRITE=1 BUS_EN : IN STD_LOGIC:='0'; -- CHIP ENABLE BUS_BUSY : OUT STD_LOGIC:='0'; -- '1' WHEN REGISTER IS WRITING DATA TO GLOBAL BUS BUS_ADDR : IN STD_LOGIC_VECTOR(ADDR_WIDTH-1 DOWNTO 0):=(OTHERS=>'0'); --BUS ADRESSE DOUT : OUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0):=(OTHERS=>'0'); --REGISTER DATA OUT DIN : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0):=(OTHERS=>'0'); -- REGISTER DATA IN BUS_DATA : INOUT STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0):=(OTHERS=>'Z'); --DATA OUTPUT TO CONTROLLER BUS_DATA_INPUT : IN STD_LOGIC_VECTOR(DATA_WIDTH-1 DOWNTO 0):=(OTHERS=
in „2 Clock Domains, signale verbinden“ · FPGA, VHDL & Co. ·
-
Datei
clkgen.vhd
11" => -- 3 Hz ClkLeft <= Clk3Hz; SignalLeft <= Clk3Hz; when others => ClkLeft <= PulseLeft; SignalLeft <= PulseLeft; end case; -- Erzeugung der Signale fuer Generator Right case ClkModeRight is when "00" => ClkRight <= PulseRight; -- Pulse SignalRight <= PulseRight
-
Datei
uart_tx.vhd
STD_LOGIC; -- Reset. rst : IN STD_LOGIC; -- 'High' if transmitter shall start to send tx_byte. -- 'Low' when nothing should be send. tx_ack : IN STD_LOGIC; -- Data byte to be send. tx_data : IN STD_LOGIC_VECTOR(7 DOWNTO 0); -- 'High' if transmitting process has started. -- 'Low' when system is in idle mode
in „UART Kommandos funktionieren nicht“ · FPGA, VHDL & Co. ·
-
PDF
54600-Series_Datasheet__5968-8152EN_.pdf
, 8, 16, 32, 64 … to 16383 High Resolution Mode 54621A/D, 54622A/D, 54624A: 12 bits of resolution when ≥500 µs/div, (average mode with ave = 1) 54641A/D, 54642A/D: 12 bits of resolution when ≥100 µs/div, (average mode with ave = 1) Filter Sinx/x interpolation (single shot BW = sample rate/4 or bandwidth
-
PDF
vhdl.pdf
"0110" => LED := "0111111"; when "0111" => LED := "1100010"; when "1000" => LED := "1111111"; when "1001" => LED := "1110111"; when others => LED := "-------"; don’t care: std_logic_1164 end case; case SEL is 4-fach Multiplexer when "00" => O <= A; when "01" => O <= B; when "10" => O <= C; when others => O <= D; end case; 32 5.1 Anweisungen Loop Modellierung verschiedener Schleifen. Neben der Vereinfachung von Ausdrucken,¨ lassen sich so auch Wiederholungen
-
Datei
VHDL_Code_Gustl__2.txt
downto 0) ); end SOURCE; architecture Behavioral of SOURCE is signal COUNT : unsigned(9 downto 0):=(others => '0'); signal SCHALTER_GRENZE : unsigned(9 downto 0):=(others => '0'); --wie mach ich das SCHALTER_GRENZE den Wert von Schalter Eingang übernimmt ? begin -- Vieleicht so ? SCHALTER_GRENZE <= SCHALTER
-
Datei
SOURCE.vhd
downto 0) ); end SOURCE; architecture Behavioral of SOURCE is signal COUNT : unsigned(9 downto 0):=(others => '0'); signal Schalter_grenze : unsigned(9 downto 0):=(others => '0'); begin Schalter_grenze <= unsigned(SCHALTER(9 downto 0)); -- Hier hab ich es umgewandelt process (CLK) begin if rising_edge(CLK
-
Datei
lpout.diff
@ --- "*" and "+" differs only in bit 0 so this bit can be ignored - case lpbits(6 downto 1) is - when "010101" => store <= '1'; - when others => store <= '0'; + case lpbits is + when "0101011" => store <= '1'; setbusy <= '1'; + when "0101010" => store <= '1'; setbusy <= '0'; + when others => store <
in „Einfaches CPLD-Beispiel für Xilinx?“ · FPGA, VHDL & Co. ·
-
Datei
fsm_01.vhd
process Z_SPEICHER; FSM: process --(CLK_FSM,State) begin wait until rising_edge(CLK_FSM); case State is when z0 => sAc_reg <=(others=>'0'); sBs_reg <=(others=>'0'); senSPI <= '0'; senCordic <= '0'; when z1 => senSPI <= '1'; senCordic <= '0'; when z2 => senSPI <= '0'; senCordic <= '1'; sAc_reg <= (Spi_c - haelfte); sBs_reg <= (Spi_s - haelfte); end case; end process FSM; Cos_Cor <= signed(sAc_reg);-- when senCordic = '1'; Sin_Cor <= signed(sBs_reg);-- when senCordic = '1'; EnSpi <= senSpi; EnCor <= senCordic; end fsm_01;
-
Datei
multiply.vhd
mb_next <= mb; result_next <= result; count_next <= count; -- default done <= '0'; case state is when IDLE => if edge = '1' then next_state <= ADD; count_next <= 2; ma_next <= unsigned( multiplicand); mb_next <= resize( unsigned( multiplier), mb'length); result_next <= ( others => '0'); end if; when
in „Sequential System Design Using ASM Charts“ · FPGA, VHDL & Co. ·
-
Datei
dma.vhdl
busy signal io_busy : std_logic; -- Shadows: signal s_addr_src : unsigned(ADDR_W-1 downto 0) := (others => '0'); signal s_addr_dst : unsigned(ADDR_W-1 downto 0) := (others => '0'); signal count : unsigned(16-1 downto 0); type dma_state_t is ( S_IDLE, S_START, S_RUNNING, S_DONE ); signal state : dma_state_t
in „Wie größeres FPGA Projekt aufbauen“ · FPGA, VHDL & Co. ·
-
PDF
vhdl.pdf
"0110" => LED := "0111111"; when "0111" => LED := "1100010"; when "1000" => LED := "1111111"; when "1001" => LED := "1110111"; when others => LED := "-------"; don’t care: std_logic_1164 end case; case SEL is 4-fach Multiplexer when "00" => O <= A; when "01" => O <= B; when "10" => O <= C; when others => O <= D; end case; 32 5.1 Anweisungen Loop Modellierung verschiedener Schleifen. Neben der Vereinfachung von Ausdrucken,¨ lassen sich so auch Wiederholungen
-
Datei
time_ms.vhd
std_logic_vector(1 downto 0) ) return std_logic_vector is variable ms_outp : std_logic_vector(3 downto 0) := (others => '0'); variable ms_outp_lcd : std_logic_vector(8 downto 0) := (others => '0'); begin ms_outp_lcd(7 downto 4) := x"3"; case sel_par is when "00" => ms_outp := time_16bit mod 10; when "01" => ms_outp := (time_16bit / 10) mod 10; when "10" => ms_outp := (time_16bit / 100) mod 10; when "11" => ms_outp := (time_16bit / 1000); end case; ms_outp_lcd(3 downto 0) := ms_outp; return ms_outp_lcd; end to_time_ms; end time_ms;
in „VHDL function für Umwandlung eines 16Bit Wertes??“ · FPGA, VHDL & Co. ·
-
Datei
VHDL_Code_Gustl.txt
downto 0) ); end SOURCE; architecture Behavioral of SOURCE is signal COUNT : unsigned(9 downto 0):=(others => '0'); signal COUNT_SCHALTER : unsigned(3 downto 0):=(others => '0'); --Schalter Zaehler nur 4 Bit weil mehr braucht ich derzeit ned weil 13 signal SCHALTER_GRENZE : unsigned(3 downto 0):="1101";
-
Datei
SOURCE.vhd
downto 0) ); end SOURCE; architecture Behavioral of SOURCE is signal COUNT : unsigned(9 downto 0):=(others => '0'); signal Schalter_grenze : unsigned(9 downto 0):=(others => '0'); begin Schalter_grenze <= unsigned(SCHALTER(9 downto 0)); -- Hier hab ich es umgewandelt --DATA_OUT <= DATA_IN; Hier hatte ich
-
PDF
vhdlqrc.pdf
sequential_statement}] italic VHDL-1993 end [procedure] ID]; 2.1. T YPE DECLARATIONS for LABELID | others | all : COMPID use 1. L IBRARY U NITS type ID is ( {ID,} ); (entity [LIBID.]ENTITYID [( ARCHID )]) | type ID is range number downto | to number; (configuration [LIBID.]CONFID) [{use_clause}] [[generic
-
PDF
MOC3052M-D.PDF
except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98AON13450G Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: PDIP6 8.51x6.35, 2.54P PAGE
in „Phasenanschnitt-Steuerung funktioniert nicht“ · Analoge Elektronik und Schaltungstechnik ·
-
PDF
MOC3052M-D.PDF
except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98AON13450G Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: PDIP6 8.51x6.35, 2.54P PAGE
in „Leistung für Gatewiderstand Triac“ · Analoge Elektronik und Schaltungstechnik ·
-
Datei
LCD_CTRL.vhd
incrementieren x"0C", -- Display ein, Unterstrich-Cursor, Cursor ein x"02", -- Cursor Home, Zeile oben others => x"01" -- Clear Display -- others => (std_logic_vector(to_unsigned(character'pos('X'),8))) ); attribute ram_style: string; attribute ram_style of ram : signal is "block"; signal index : integer range
-
Datei
VHDL.txt
segm <= "00000110" when sync = '1' else "00111111"; --Sync-Signal anzeigen segm2<="00000110" when current = '1' else "00111111"; --aktuelles Bit anzeigen TIMER: process(clk, res) begin if res='0' or sig='0' then --Zähler rücksetzen
-
Datei
ram_converter_2.vhd
-- yes, we do a write access sram_wr <= '0'; else -- no, no write access sram_wr <= '1'; end if; when "01" => sram_rd <= '1'; -- write access, hold time sram_wr <= '1'; sram_data <= data_wr; sram_adr <= adr_wr; when "11" => sram_rd <= '0'; -- read access sram_wr <= '1'; sram_data <= (others=>'Z'); sram_adr <= fpga_adr; when others => null; end case; end process; process(fpga_clk) begin if rising_edge(fpga_clk) then tog <= not tog; fpga_di <= sram_data; -- read data register adr_wr <= fpga_adr; -- store for write access
-
Datei
FIRFilter.vhd
1) of std_logic_vector(2 * DSIZE - 1 downto 0); -- 48 Bit Akkumulator --signal a_sop : ASOP := ( others => x"000000000000" ); type ASOP is array (0 to NBTAP - 1) of signed(2 * DSIZE - 1 downto 0); -- 48 Bit Akkumulator signal a_sop : ASOP := ( others => x"000000000000" ); type ACOEF is array (0 to NBTAP
in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·
-
Datei
ps2_mouse.vhdl
(not ps2_data) = '1') then m2_next_state <= "1010"; else m2_next_state <= "1011"; end if; end if; when "1111" => error_no_ack_Reg <= '1'; m2_next_state <= "1111"; when "1010" => if Resize(bit_count, 7) = "0010110" then m2_next_state <= X"3"; else m2_next_state <= "1010"; end if; when others => m2_next_state
-
Datei
sin_gen.vhd
x"7e", x"7e", x"7e", x"7f", x"7f"); begin Sign_Quadrant <= Sign & Quadrant; case Sign_Quadrant is when "10" => Result_sin2 <= Sinus_Rom ( to_integer(Address)); Data_sin2 <= Result_sin2; when "11" => Result_sin2 <= Sinus_Rom (63-to_integer(Address)); Data_sin2 <= Result_sin2; when "00" => Result_sin2 <= Sinus_Rom ( to_integer(Address)); Data_sin2 <= std_logic_vector (-signed(Result_sin2)); when "01" => Result_sin2 <= Sinus_Rom (63-to_integer(Address)); Data_sin2 <= std_logic_vector (-signed(Result_sin2)); when others => null; end case; if(Quadrant='0') then Result_sin1 <= Sinus_Rom ( to_integer
-
Datei
gen_tick.vhd
integer:= integer(ceil(log2(real(DVSR-1)))); signal ms_next, ms_reg: unsigned(swidth downto 0) := (others=>'0'); begin -- register process (clk, reset) begin if (reset = '1') then ms_reg <= (others=>'0'); elsif rising_edge(clk) then ms_reg <= ms_next; end if; end process; -- next state logic ms_next <= (others=>'0') when ms_reg=(DVSR-1) else ms_reg + 1; tick <= '1' when ms_reg=(DVSR-1) else '0'; end RTL;
in „gh_fifo_sync_sr: loadless signals?“ · FPGA, VHDL & Co. ·
-
Datei
SerialMultiplier.vhd
partialProduct : std_ulogic_vector(multiplicand'high + 1 downto 0) := (others => '0'); signal lowProductShiftReg : std_ulogic_vector(multiplicator'range) := (others => '0'); signal processingShiftReg : std_ulogic_vector(multiplicator'high + 1 downto 0) := (others => '0'); signal
in „Signal auf bestimte Range von Port mappen“ · FPGA, VHDL & Co. ·
-
Datei
Memory_Controller.vhd
then delay <= delay + 1; else delay <= 0; internal_FPGA_nWE <= '1'; state_reg <= FPGA_wr3; end if; when FPGA_wr3 => if (delay < WAITSTATES) then delay <= delay + 1; else delay <= 0; state_reg <= idle; end if; when FPGA_rd1 => internal_FPGA_nOE <= '0'; internal_RAM_done <= '0'; state_reg <= FPGA_rd2; when
in „Sram Simulation funktioniert nicht richtig“ · FPGA, VHDL & Co. ·
-
Datei
top.vhd
<= startup; end if; when startup => debug <= NOT "01100000"; --debug <= NOT std_logic_vector(to_unsigned(state_t'pos(status),8)); if (delay <= CLOCK) then delay <= delay + 1; status <= startup; else status <= running; end if; when running => debug <= NOT "00011100"; --debug <= NOT std_logic_vector(to_unsigned(state_t'pos(status),8)); status <= running; when others => debug <= NOT "00000001"; --debug <= NOT std_logic_vector(to_unsigned
in „Statemachine springt in falsche "states" warum?“ · FPGA, VHDL & Co. ·
-
Datei
ether_speed.vhd
speed_detect; architecture behavioral of speed_detect is signal countertx: unsigned (2 downto 0):=(others=>'0'); signal counterrx : unsigned (2 downto 0):=(others=>'0'); begin -- here is testing if GMII aktive or not? -- algorithm -- in GMII RX-clk has 125MHz -- Now the question run RX-clk in with a higher
-
Datei
ITPModul_tb.vhd
Koordinate Z signal tb_XT : std_logic_vector(31 downto 0) := (others => '1'); -- Koordinate X relativ (XE-XS) signal tb_YT : std_logic_vector(31 downto 0) := (others => '1'); -- Koordinate Y relativ (YE-YS) signal tb_ZT : std_logic_vector(31 downto 0) := (others =>
-
Datei
Fifo.vhd
unsigned (Addrbreite-1 downto 0) := (others => '0'); signal rdcnt : unsigned (Addrbreite-1 downto 0) := (others => '0'); type speicher is array(0 to (2**Addrbreite)-1) of unsigned(Wortbreite-1 downto 0); signal memory : speicher; signal full_loc
in „Frage zu fifo“ · FPGA, VHDL & Co. ·
-
Datei
exmple.vhd
CLK) begin if CLK'event and CLK = '1' then if Koeffi_WR = '1' and WR = '0' then case Koeffi_Adr is when b"000" => Koeffi_0 <= Koeffi_in; when b"001" => Koeffi_1 <= Koeffi_in; when b"010" => Koeffi_2 <= Koeffi_in; when others => null; end case; WR <= '1'; elsif Koeffi_WR = '0' then WR <= '0'; end if; end
in „Regelkreis“ · FPGA, VHDL & Co. ·
-
Datei
la.vhd
)) (95 downto 64); when "10" => BBUS_out.BRDATA<=fifo(to_integer(unsigned( BBUS_IN.BADDR(13 downto 4)) +trigger_pos)) (63 downto 32); when "11" => BBUS_out.BRDATA<=fifo(to_integer(unsigned( BBUS_IN.BADDR(13 downto 4)) +trigger_pos)) (31 downto 0); when others =>NULL; END CASE; end if; end process; BBUS_out.BREADYOUT <= '1'; end Behavioral;
-
Datei
uart.vhd
; end if; when TX_STATE_TRANSMIT => if ce_tx = '1' then if tx_bit_cnt = WIDTH+1 then tx_state <= TX_STATE_IDLE; tx_busy <= '0'; else tx <= tx_data(tx_bit_cnt); tx_bit_cnt <= tx_bit_cnt + 1; end if; end if; end case
in „[Anfänger] RS232 Modul in VHDL - Kritik erwünscht“ · FPGA, VHDL & Co. ·
-
Datei
drehgeber.vhd
:= '0'; begin wait until rising_edge(CLK_50MHZ); cu := '0'; -- lokale Werte cd := '0'; case z is when Z00 => if (e = "01") then z <= Z01; cu := '1'; elsif (e = "10") then z <= Z10; cd := '1'; end if; when Z01 => if (e = "11") then z <= Z11; cu := '1'; elsif (e = "00") then z <= Z00; cd := '1'; end if; when Z11 => if (e = "10") then z <= Z10; cu := '1'; elsif (e = "01") then z <= Z01; cd := '1'; end if; when Z10 => if (e = "00") then z <= Z00; cu := '1'; elsif (e = "11") then z <= Z11; cd := '1'; end if
in „Signal von Drehgeber nicht erkannt“ · FPGA, VHDL & Co. ·
-
Datei
Segmentanzeige.vhd
SegmentVector0 : std_logic_vector (6 downto 0):= "0000000"; begin if Rst = '1' then AllSegments := (Others => '1'); SegmentVector0 := (Others => '0'); elsif rising_edge(En) then ASCIICheckSegment(Ergebnis,SegmentVector0); AllSegments := SegmentVector0 & AllSegments(27 downto 7); end if; end process; Segmente
in „RS232 Daten Empfangen, Vergleichen, auf Monitor ausgeben (SPARTAN 3)“ · FPGA, VHDL & Co. ·
-
PDF
ATxmega_schematic.pdf
for very low power consumption, and thus when selecting crystals, see Table 4-3 for maximum ESR recommendations on 9 pF and 12.5 pF crystals. The Low-frequency Crystal Oscillator provides an internal load capacitance of typical 8.0 pF. Crystals
in „Stromversorgung XMega“ · Mikrocontroller und Digitale Elektronik ·
-
Datei
EthernetTX.vhd
'0'; nextState <= stSendPayloadLowNybble; when others => end case; else nextState <= stSendHeader; if counter(4 downto 0) >= '1' & x"9" then -- when the tx_clk is high, use the time to latch tx data nextTxData <= txData2; nextTxData2 <= txData3;
in „100MBit Ethernet mit Spartan 3E Starter Kit“ · FPGA, VHDL & Co. ·
-
Datei
CosFP.vhd
RANGE 0 TO 7:= 0; BEGIN IF rising_edge(clk) THEN IF nrst = '0' THEN state := 0; cntrclk := 0; --(OTHERS => '0'); ELSE CASE state IS WHEN 0 => IF cecos = '1' THEN ce1 <= '1';-- start für 1-x, x`2, ComP0.5 state := 1; ELSE state := 0; END IF; WHEN 1 => --- Ausführen ain :=ainp^2 ce1 <= '0'; ce2 <= '1';-- start für fkt_c cntrclk := 11; state := 2; WHEN 2 => ---- mul2mX,2powX fertig IF cntrclk = 0 THEN state := 0;--warten auf nächste Start ELSE ce2 <= '0'; cntrclk := cntrclk -1; state := 2; END IF; WHEN OTHERS => state := 0; END CASE; END IF; -- if
-
Datei
atari_tb.vhd
Refreshausgang, um eigene Zugriffe auf den Bus zu ermöglichen (über BC847 Transistor) begin tb_data <= ( others => 'Z'); tb_ram_rom_adr <= ( others => 'Z'); tb_rdy <= '0'; tb_switch_in <= '0'; tb_phi2 <= not tb_phi2 after tb_phi2_period / 2 when simulation_run; tb_reset_n_in <= '0', '1' after 10 * tb_phi2_period; tb_clk50 <= not tb_clk50 after tb_clk50_period / 2 when simulation_run; tb_gpio <= ( others => 'Z'); tb_gpin <= "00"; process begin wait until rising_edge( tb_phi2); tb_phi2short <= '1'; wait for tb_phi2_period * 1 / 3; tb_phi2short <= '0'; if not simulation_run
-
Datei
SerialMultiplier.vhd
) := (others => '0'); signal lowProductShiftReg : unsigned(multiplicator'range) := (others => '0'); signal processingShiftReg : unsigned(multiplicator'high + 2 downto 0) := (others => '0'); signal lastNewData :
in „Signal auf bestimte Range von Port mappen“ · FPGA, VHDL & Co. ·
-
Datei
sixcounter.vhd
debounce_type is array(0 to 5) of std_logic_vector(2 downto 0); signal debsr : debounce_type := (others=>(others=>'0')); -- 6 Stück 32 Bit Zähler als Array definieren type counter_type is array(0 to 5) of unsigned(31 downto 0); signal cnt : counter_type := (others=>(others=>'0')); -- der Schattenspeicher
in „Mehrkanal Impulszähler PIC“ · Mikrocontroller und Digitale Elektronik ·
-
Datei
uart.vhd
<= clk_count_tx + 1; ce_tx <= '0'; else clk_count_tx <= 0; ce_tx <= '1'; end if; case tx_state is when TX_STATE_IDLE => -- Reset data tx_bit_cnt <= 0; clk_count_tx <= 0; tx_data <= '1' & din; if tx_start = '1' then tx_busy <= '1'; -- Write start bit tx <= '0'; tx_state <= TX_STATE_TRANSMIT; end if; when
in „[Anfänger] RS232 Modul in VHDL - Kritik erwünscht“ · FPGA, VHDL & Co. ·
-
PDF
lab11.pdf
<= S1; else y1 <= '1'; next_state <= S0; end if; when others => next_state <= S0; end case; end process; OUTPUT_DECODE : process (state) begin ya <= '0'; yb <= '0'; yc <= '0'; case (state) is when S0 => ya <= '1'; when S1 => yb <= '1'; when S2 => yc <= '1'; when others => ya <= '0'; yb <= '0'; yc <= '0'; end case; end process; Artix-7 11-4 www.xilinx.com/university xup@xilinx.com © copyright 2015 Xilinx Lab Workbook Sequential System Design Using ASM Charts
in „Sequential System Design Using ASM Charts“ · FPGA, VHDL & Co. ·
-
Datei
echo_on_uart.vhd
; -- this should not be reached end if; when S2 => StateTest <= x"2"; -- debug only SMRun <= '1'; -- indicate running state machine if (TXR = '1') then TXOut <= TXOBuf; TXEn <= '1'; NState <= S3; else NState <= S2; NULL; NULL; end if; when S3
-
Datei
artix_ftdi_fifo0.vhd
STD_LOGIC; empty : OUT STD_LOGIC); END component; signal blinkcounter_60: unsigned(25 downto 0):=(others => '0'); signal WR_buff, TXE_buff, fail: std_logic:='0'; signal fifo_full, fifo_empty, fifo_empty_buff, fifo_rd, fifo_rd_buff, fifo_wr: std_logic:='0'; signal send_byte: unsigned(7 downto 0):=(others
-
PDF
MOC3083M-D.pdf
except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98AON13450G Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: PDIP6 8.51x6.35, 2.54P PAGE
in „Alte Triacschaltung umbauen“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
DTC114EP-D.PDF
may not follow the Generic Marking. STYLES ON PAGE 2 Electronic versions are uncontrolled except when accessed directly from the Document Repository. DOCUMENT NUMBER: 98ASB42985B Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. DESCRIPTION: SC−88 2.00x1.25x0.90, 0.65P
in „Kollektorschaltung statt KFZ Relais“ · Analoge Elektronik und Schaltungstechnik ·
-
Datei
FIFO_async.vhd
next_bin_waddr<=bin_waddr+1; end process; rbin:process (rclk,rst_n) begin if rst_n='0' then bin_raddr<=(others=>'0'); elsif (rclk'event and rclk='1') then if rd='1' and fifo_empty='0' then bin_raddr<=next_bin_raddr; end if; end if; end process; process (rclk,rst_n) begin if rst_n='0' then rgray<=(others=>'0