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Schaltpläne und Blockschaltbilder eines DDS/PLL-Systems
BIT x 40 SERIAL DATA, RESET, W_CLK AND FQ_UD IOUT 470pF 100kΩ 200Ω LOW-PASS FILTER IOUTB 100Ω 200Ω AD9851 CMOS OUTPUTS QOUT QOUTB RSET 3.9kΩ 180MHZ OR 30MHZ REFERENCE CLOCK VOLTAGE HERE = CENTER POINT OF SINE WAVE (0.5V TYPICALLY) USING PASSIVE AVERAGING CIRCUIT 0 TO 1V p-p SINE WAVE Figure 2. Basic Clock
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Schaltplan und Tabelle für AD9851 Clock Generator
AD9851 MICROPROCESSOR OR MICROCONTROLLER DATA BUS 8-BIT PARALLEL DATA, OR 1-BIT x 40 SERIAL DATA, RESET, W_CLK AND FQ_UD IOUT 470pF 100kΩ 200Ω LOW-PASS FILTER 7TH ORDER ELLIPTICAL 70MHz LOW PASS 200Ω IMPEDANCE 0 TO 1V P-P SINE WAVE IOUTB AD9851 CMOS OUTPUTS 180MHz OR 30MHz REFERENCE CLOCK RSET 3.9kΩ QOUT QOUTB Figure 2. Basic Clock Generator Configuration COMPARATOR OUTPUT CHARACTERISTICS Logic 1 Voltage 5 V Supply 25°C VI 4.8 V Logic 1 Voltage
