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Leiterplatten-Layout eines Mikrocontroller-Designs
C82 C3 C1 PIC32 C4 R128 C5 C6 R2 R15 C9 C15 C14 R16 R18 R19 R17 R20 R21 R22 R8 C19 R C18 R5 C2 R6 R13 C13 DATA1 Ethernet SPEED1 LINKED1 C16 R14 R12 R25 R24 3V3 3V3 C17 LAN M2 M1 X3
in „Umstieg auf 6 Lagen? Welche Signale wohin?“ · Platinen · · Layouts
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emac.c
definitions. */ #if (PHY_ID == LAN8720_ID) #define emacLINK_ESTABLISHED ( 0x0004 ) #elif (PHY_ID == DP83848C_ID) #define emacLINK_ESTABLISHED ( 0x0001 ) #else #error "unsupported PHY" #endif #define emacFULL_DUPLEX_ENABLED ( 0x0004 ) #define emac10BASE_T_MODE ( 0x0002 ) #define emacPINSEL2_VALUE 0x50150105
in „uIP doppelte Replys“ · Mikrocontroller und Digitale Elektronik ·
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emac.c
Floating on Reset) CheckPHYAddr(); Seriell_Text("\r\nPHY_ADDR:"); Seriell_IntToHex(phyAddr); /* Put the DP83848C in reset mode */ write_PHY (PHY_REG_BMCR, 0x8000); //write_PHY (PHY_REG_BMCR, 0x8000); /* Wait for hardware reset to end. */ iStep = 3; case 3: regv = read_PHY (PHY_REG_BMCR); if ((regv & 0x8000)) return 0; /* Check if this is a DP83848C PHY. */ id1 = read_PHY (PHY_REG_IDR1); id2 = read_PHY (PHY_REG_IDR2); DWORD id3 = (((DWORD)id1 << 16) | (id2 & 0xFFF0)); phyTyp = 0; if ((id3 & DP83848C_ID) == DP83848C_ID) phyTyp = 1; else if ((
in „STM32F207 + KS8721 (Ethernet Phy)“ · Mikrocontroller und Digitale Elektronik ·
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ethernet_application.c
Configure the PHY to generate an interrupt on change of link status */ Ethernet_Link_PHYIT_Config(DP83848_PHY_ADDRESS); /* Configure the EXTI for Ethernet link status. */ Ethernet_EXTI_Config(); return SUCCESS; } void Ethernet_GPIO_Config(void) { /* Ethernet pins configuration ************************
in „STM32F207 Ethernet + RMII“ · Mikrocontroller und Digitale Elektronik ·
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hardware_profile.h
) #define SYS_XTAL_FREQ 25000000 // external Xtal, Hz #define PHY_ADDRESS 0x1 // address our NAT DP83848C PHY is mapped to #elif defined (EXPLORER16) #define SYS_XTAL_FREQ 8000000 // external Xtal, Hz #else #define SYS_XTAL_FREQ 25000000 // external Xtal, Hz #define PHY_ADDRESS 0x1 // address our NAT DP83848C PHY is mapped to #endif /***************************************************************************** * The number of ticks per second. This is used to define timeouts * and must be defined before
in „TCP/IP Stack PIC32“ · Mikrocontroller und Digitale Elektronik ·
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stm32f1xx_hal_conf.h
uint32_t)4) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ /* Section 2: PHY configuration section */ /* DP83848_PHY_ADDRESS Address*/ #define DP83848_PHY_ADDRESS 0x01U /* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ #define PHY_RESET_DELAY ((uint32_t)0x000000FF) /* PHY Configuration
in „[Pollin] Grafik Display Anschluss Verständnisfragen“ · Mikrocontroller und Digitale Elektronik ·
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S7-1200-Hardware.pdf
OUTPUTS E AJOD HB541 HB541 RJ45 Buchse Ethernet PHY SPANSION National Semiconductor S29JL064H70TF100 DP83848VV 127FF466 G 64 Megabit (8 M x 8-Bit/4 M x 16-Bit) WE Simultaneous Read/Write Flash Memory 749010012 1052 Ethernet Übertrager Rückseite JM14AC LM25116 MH HA541 OCTAL BUFFERS/DRIVERS WITH 3- Wide Range
in „Prozessortyp in einem SoC herausfinden“ · Mikrocontroller und Digitale Elektronik ·
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stm32f4x7_eth_bsp.h
---------------------------------------------*/ extern uint16_t lan8710a_phy_addr; // // #define DP83848_PHY_ADDRESS 0x01 /* Relative to STM324xG-EVAL Board */ /* Ethernet Flags for EthStatus variable */ #define ETH_INIT_FLAG 0x01 /* Ethernet Init Flag */ #define ETH_LINK_FLAG 0x10 /* Ethernet Link Flag
in „STM32-E407 Ethernet / UDP“ · Mikrocontroller und Digitale Elektronik ·
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eth_conf.h
update this value depending on the used external PHY */ #define PHY_SR ((uint16_t)31) /* Value for DP83848 PHY */ /* The Speed and Duplex mask values change from a PHY to another, so the user have to update this value depending on the used external PHY */ #define PHY_DUPLEX_SPEED_STATUS_MASK ((uint16_t
in „stm32f4xx lan8720 uip“ · Mikrocontroller und Digitale Elektronik ·
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AES-S6MB-LX9-G_SCH_RevC.PDF
06037 4.7uF 6.3V 0402 P0 0.22uF 6.3V 0201 Place power decoupling GND capacitors close to the +3.3V DP83848J. DP83848J.istors and capacitors close to P219 C216 020 P0.7uF 6.3V 0C62 0.22uF 6.21 0201 0.22uF 6.3V 0201 +3.3V +3.3V C30 2 32C311 GND 8 7 6 5 +3.3V 0.22uF 6.3V 0201 RP22 300.22uF 6.3V 0201 P1 49R9 +3.3V +3.3V R6 U66 GND GND 1K50 0402 1 2 8 9 1 18DP83848J 71 B U8691 1 2 3 4 R27 B P2 3 3 1 2 3 3 013 4 Route TD+/- and RD+/- as 100-120 300R 0402 5OF PGA_ETH_MDC FPGA_ETH_MDIO 25MHz Max PIU2425MDC D D V V V D ohm differential pairs. 11 J1 1270 5OFF GA_ETH_MDIOO
in „Pulse Generator nicht genau genug, brauche Hilfe“ · FPGA, VHDL & Co. ·
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Datei
stm32f4x7_eth_conf.h
**** PHY Extended Registers section : ************************/ /* These values are relatives to DP83848 PHY and change from PHY to another, so the user have to update this value depending on the used external PHY */ #if defined(SMSC_LAN8710A_PHY) /* The LAN8710A PHY status register */ #define PHY_SR
in „STM32-E407 Ethernet / UDP“ · Mikrocontroller und Digitale Elektronik ·
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FPGA_Kits_Vergleich_120205.pdf
- - Flash - 16MB parallel - 16MB StartaFlash Intel 16MB StartaFlash Intel - Ethernet 10/100 PHY DP83848J 10/100 PHY LAN8710 10/100/1000 PHY 10/100 PHY - - Marvell M88E1111 SMSC LAN83C185 RS232 - - - Two 9-pin (DTE and DCE) Two 9-pin (DTE and DCE) - USB-A plug Micro-AB High speed Micro-AB High speed
in „Vergleich und Erfahrung zu LX9 MicroBoard, Nexys 3 und Atlys“ · FPGA, VHDL & Co. ·
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F407-IoTBoard-Schematics.pdf
IIC_SDA R18 4.7K GND GND D6 USB_M USB_HS_DP 10R HS_DP AT24Cxx VCC3.3 GND B GND R60 B . C29 104 网口-DP83848 SRAM U6 RS485 C GND VCC3.3 L2 VCC3.3E FSMC_A0 5 38 FSMC_D15 U7 C R19 VCC3.3E C30 C31 C32 C33 C34 C35 FSMC_A1 4 A0 D15 37 FSMC_D14 485_TX 1 8 V R20 360R 360R 2 2 2 2 10uH FSMC_A2 3 A1 D14 36 FSMC_D13
in „STM32 Nucleo welches Board am besten?“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Ethernet.c
; /* Configure the PHY to generate an interrupt on change of link status */ Eth_Link_PHYITConfig(DP83848_PHY_ADDRESS); /* Configure the EXTI for Ethernet link status. */ Eth_Link_EXTIConfig(); } static void ETH_MACDMA_Config(void) { ETH_InitTypeDef ETH_InitStructure; /* Enable ETHERNET clock */ //RCC_AHB1PeriphClockCmd
in „STM32F207 + KS8721 (Ethernet Phy)“ · Mikrocontroller und Digitale Elektronik ·
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lpc17xx_emac.c
LPC_EMAC->SUPP = EMAC_SUPP_RES_RMII; for (tout = 100; tout; tout--); LPC_EMAC->SUPP = 0; /* Put the DP83848C in reset mode */ write_PHY (EMAC_PHY_REG_BMCR, EMAC_PHY_BMCR_RESET); /* Wait for hardware reset to end. */ for (tout = EMAC_PHY_RESP_TOUT; tout; tout--) { regv = read_PHY (EMAC_PHY_REG_BMCR); if
in „LPC1768 Ethernet mit DP83848J“ · Mikrocontroller und Digitale Elektronik ·
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XCore407I.pdf
JPAD B PB11 ETH2_JP 2 TX_ENE 3 3 3 3 3 3 3 2 2 2 2 2 U1_838438 PJPAD20JP202 PIETH20JP201 1 2 3 0 1 DP83848I N N X X D DD T A A _OU UPIU10RPIU10RGND 3.3V TX_DPG1G4 ETH2_JP3 D I V MM S K D Az_ U1_R7R 150R COU10C12 PIJPAD0JP302 PIETH20JP301 I R L P OM PIU10RPIU10R702 PIU10C1202 PIU10C1201 ETH2_JP 4 TX_D1D
in „STM32 Board von Waveshare“ · Mikrocontroller und Digitale Elektronik ·
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5_-_STM32F_Connectivity_Line.pdf
RMII_REF_CLK Input 50MHz 50MHz TIM2TriggeTime Stamp MDIO Comparator MDC 50MHz MCO XT1/XT2 OSC PLLs NS DP83848 * XTAL * The NS DP83848 is recommended as the 25MHz input jitter requirement of this PHY is cospecification of the MCUjitter ST M 32S e m inarN ov em ber2 0 10 40 Media Access Controller: MAC Features
in „STM32: Timer funktioniert nicht“ · Mikrocontroller und Digitale Elektronik ·
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stm32f107.c
-----*/ /* Private define ------------------------------------------------------------*/ #define DP83848_PHY /* Ethernet pins mapped on STM3210C-EVAL Board */ #define PHY_ADDRESS 0x01 /* Relative to STM3210C-EVAL Board */ //#define MII_MODE /* MII mode for STM3210C-EVAL Board (MB784) (check jumpers setting
in „STM32 System_Setup“ · Mikrocontroller und Digitale Elektronik ·
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landtiger_v2.0_-_manual__v1.1.pdf
32.768 kHz crystal, is the clock source for the RTC. U4, 50MHZ crystal, is the Ethernet PHY chip DP83848 clock. LandTiger V2.0 User Manual 7 Y3, 8 MHz is the clock for the JLink Debugger interface Note 1: See section 2.1 on powersupply and onboard battery backup for the RTC. 2.3 Reset Mode The reset
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STM32F2X7VGT6-DK-A.pdf
15 R2 0 GND 37 RBIAS AGND 47 4.87K 18 PFBIN IOGND 35 23 PFBIN IOGND 36 PFBOUT DGND C7 C8 C9 C10 DP83848CVV GND 0.1uF 0.1uF 0.1uF 0.1uF GND A A Title Size Number Revision B Date: 20-Jul-2011 Sheet of File: E:\Mywork\ARM\STM32F2x7\Schematic\Sra3w2xy7:VG.ddb 1 2 3 4 5 6 1 2 3 4 5 6 U3 J2 +5V AS1117-3.3
in „STM32F207 Ethernet + RMII“ · Mikrocontroller und Digitale Elektronik ·
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STM32F2X7VGT6-DK-A.pdf
15 R2 0 GND 37 RBIAS AGND 47 4.87K 18 PFBIN IOGND 35 23 PFBIN IOGND 36 PFBOUT DGND C7 C8 C9 C10 DP83848CVV GND 0.1uF 0.1uF 0.1uF 0.1uF GND A A Title Size Number Revision B Date: 20-Jul-2011 Sheet of File: E:\Mywork\ARM\STM32F2x7\Schematic\Sra3w2xy7:VG.ddb 1 2 3 4 5 6 1 2 3 4 5 6 U3 J2 +5V AS1117-3.3
in „STM32F2xx USART weigert sich“ · Mikrocontroller und Digitale Elektronik ·
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armbian_modules.txt
common b53_srab vitesse-vsc73xx veth enc28j60 dwmac-dwc-qos-eth hip04_eth hns_mdio icplus et1011c dp83848 dp83tc811 qsemi bcm87xx amd microchip lxt phylink at803x teranetics davicom smsc marvell aquantia micrel realtek national bcm-phy-lib microchip_t1 broadcom vitesse ste10Xp cicada plusb asix rndis_host
in „Samba auf Banana Pi Pro installieren“ · PC Hard- und Software ·
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HY-LandTiger_SCH.pdf
AGND 47 B P1.15 R49 18 PFBIN2 IOGND 35 B ENET_REF_CLK R117 23 PFBIN1 IOGND 36 0R 4.87K PFBOUT DGND DP83848CVV 3V3 C20 C21 C22 C60 C23 C24 C25 104 104 104 10uF 104 104 104 A Title A www.PowerMCU.com Size Number Revision A4 Date: 11-Dec-2010 Sheet of File: F:浩宇电子 \HY-LandTiger\LandTiger.DdbDrawn By: 1 2
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Aim_TTi_QL_Series_II_Service_Manual_48511-1740.pdf
SOT223 IC4 27163-1232 IC SM 232A RS232 DRIVER IC1 27246-0140 IC SM 74LCX14 SO14 IC5 27250-2260 IC SM DP83848C PHYTER LQFP48 IC3 27250-2340 IC SM MCU LPC2368 TFBGA100 IC2 28500-2040 XTAL SM 12MHZ 30/50PPM 16PF XTL1 28515-1000 OSC MODULE SM 50MHz ACT9300 OCS1 35594-0290 PCB I/F LAN/USB/RS232 QL PCB ASSEMBLY
in „wegen Aim TTi Netzteil Qualität“ · Analoge Elektronik und Schaltungstechnik ·
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STM32F107.pdf
Timer MDIO input MDC TIM2 triggeTime stamp comparator XTAL 50 MHz 25 MHz OSC PLLS XT1/XT2 (1) NS DP83848 ai15659b 1. The NS DP83848 is recommended as the input jitter requirement of this PHY. It is compliant with the output jitter specification of the MCU. 86/93 Doc ID 15274 Rev 3 STM32F105xx, STM32F107xx
in „STM32-comStick USB-Bootloader“ · Mikrocontroller und Digitale Elektronik ·
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mb1045_changed.pdf
6 423 P0PFBOUT DGND 36 P2JP602 C C C C 2 1 1 2 C134 P0MII0MCO PA8 P0JP603 5 C135 1 C131 6 C136 4 DP83848CVV MII_MCO 1 100nF 1 100nF 1 100nF 1 10uF P P P P JP6 D D STMicroelectronics Title: STM324x9I-EVAL Ethernet Number: MB1045 Rev: B.2(PCB.SCH) Date: 7/24/2013 Sheet 7 of 16 1 2 3 4 1 2 3 4 Place close
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mb1045_changed_korrigiert.pdf
6 423 P0PFBOUT DGND 36 P2JP602 C C C C 2 1 1 2 C134 P0MII0MCO PA8 P0JP603 5 C135 1 C131 6 C136 4 DP83848CVV MII_MCO 1 100nF 1 100nF 1 100nF 1 10uF P P P P JP6 D D STMicroelectronics Title: STM324x9I-EVAL Ethernet Number: MB1045 Rev: B.2(PCB.SCH) Date: 7/24/2013 Sheet 7 of 16 1 2 3 4 1 2 3 4 Place close
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config-mod-LK511-mt7623n-BPiR2.txt
CONFIG_DAVICOM_PHY is not set # CONFIG_DP83822_PHY is not set # CONFIG_DP83TC811_PHY is not set # CONFIG_DP83848_PHY is not set # CONFIG_DP83867_PHY is not set CONFIG_FIXED_PHY=y CONFIG_ICPLUS_PHY=y # CONFIG_INTEL_XWAY_PHY is not set # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_LXT_PHY is not set # CONFIG_MARVELL_PHY
in „Linux Kernel 5.1.1. auf dem BPi-R2“ · PC Hard- und Software ·
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kicad_8450_dcm_liste_neu_v3.pdf
25Mbps 45ns, Highest Temp. Grade, SO8 CH376T File Management USB Flash Card SD Interface, TSSOP20 DP83848C MII/RMII Single 10/100Mbps Ethernet Physical Layer Transciever, LQFP48 DS89C21 Differential CMOS Line Driver and Receiver Pair, SOIC-8 EL7242C Translateur TTL->VMOS. Double driver VMOS FUSB302B01MPX
in „KiCAD Eeschema, Bibliotheksdokumentation *.dcm als PDF-Datei“ · Platinen ·
