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Datei
RS232.vhd
<= COUNT3 + 1; WHEN OTHERS => COUNT3 <= 0; END CASE; END IF; IF (COUNT4 < 3645) THEN CASE RXD IS WHEN '1' => COUNT4 <= COUNT4 + 1; WHEN '0' => COUNT4 <= COUNT4 + 1; WHEN OTHERS => COUNT4 <= 0; END CASE; END IF; IF (COUNT5
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Datei
registerfile.vhd
" => rd <= r_r15; when others => rd <= r_r15; end case; end process; -- rs process(r_r0, r_r1, r_r2, r_r3, r_r4, r_r5, r_r6, r_r7, r_r8, r_r9, r_r10, r_r11, r_r12, r_r13, r_r14, r_r15, rs_index) begin case rs_index is when
in „ModelSim Problem 'X' anstatt '1' in std_logic_vector signal“ · FPGA, VHDL & Co. ·
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Datei
softcore.vhd
reg3_muxed; -- xor when x"C" => result <= '0' & signed(cycleCount_int(30 downto 0)); -- time when x"D" => result <= (result'left downto progCounter_act'length => '0') & signed(progCounter_act); -- pc when others => null; end case; end if; if (command(5) = '1') then -- no register modification case command(3 downto 0) is when x"1" => irpout <= '1'; -- irp when others => null; end case; end if; if (command(6) = '1') then -- jumps case command(3 downto 0) is when x"0" => -- jmp progCounter_act <= AddrOffset + progjmpaddr_fetch
in „Brainstorming Syntheselaufabhängiges Verhalten“ · FPGA, VHDL & Co. ·
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Datei
ITPModul.vhd
Stopp Exit ELSE -- kein stopp stateLinB <= S1;-- dann repeat END IF; -------------------------------- WHEN S4 => -- itp fertig stateLinB <= S5;-- normal exit -------------------------------------------- WHEN S5 => -- stop exit XLinA <= (OTHERS =>'0'); YLinA <= (OTHERS =>'0'); errX :=0; errY :=0; count :=
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Datei
ITPModul.vhd
Stopp Exit ELSE -- kein stopp stateLinB <= S1;-- dann repeat END IF; -------------------------------- WHEN S4 => -- itp fertig stateLinB <= S5;-- normal exit -------------------------------------------- WHEN S5 => -- stop exit XLinA <= (OTHERS =>'0'); YLinA <= (OTHERS =>'0'); errX :=0; errY :=0; count :=
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Datei
ITPModul.vhd
Stopp Exit ELSE -- kein stopp stateLinB <= S1;-- dann repeat END IF; -------------------------------- WHEN S4 => -- itp fertig stateLinB <= S5;-- normal exit -------------------------------------------- WHEN S5 => -- stop exit XLinA <= (OTHERS =>'0'); YLinA <= (OTHERS =>'0'); errX :=0; errY :=0; count :=
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Datei
ITPModul.vhd
Stopp Exit ELSE -- kein stopp stateLinB <= S1;-- dann repeat END IF; -------------------------------- WHEN S4 => -- itp fertig stateLinB <= S5;-- normal exit -------------------------------------------- WHEN S5 => -- stop exit XLinA <= (OTHERS =>'0'); YLinA <= (OTHERS =>'0'); errX :=0; errY :=0; count :=
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Datei
ITPModul.vhd
Stopp Exit ELSE -- kein stopp stateLinB <= S1;-- dann repeat END IF; -------------------------------- WHEN S4 => -- itp fertig stateLinB <= S5;-- normal exit -------------------------------------------- WHEN S5 => -- stop exit XLinA <= (OTHERS =>'0'); YLinA <= (OTHERS =>'0'); errX :=0; errY :=0; count :=
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Datei
AVGA.vhd
'; else VSync <= '1'; end if; end if; end if; end process; Data <= SRAM_Data; SRAM_Data <= AVR_AD when Clock = '0' and AVR_WR = '0' and Reset = '1' else (others => 'Z'); SRAM_Addr <= (others => 'Z') when Reset = '0' else Addr when Clock = '1' else "000" & AVR_AH & Latch when AVR_AH(7) = '0' else Bank
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Datei
AVGA.txt
'; else VSync <= '1'; end if; end if; end if; end process; Data <= SRAM_Data; SRAM_Data <= AVR_AD when Clock = '0' and AVR_WR = '0' and Reset = '1' else (others => 'Z'); SRAM_Addr <= (others => 'Z') when Reset = '0' else Addr when Clock = '1' else "000" & AVR_AH & Latch when AVR_AH(7) = '0' else Bank
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Datei
CIC4Stage_SM.vhd
-- 2^16 -- when x"020000" => nShift <= 68; -- 2^17 -- when x"040000" => nShift <= 72; -- 2^18 when others => nShift <= 0; end case; end if; end process Decimation; Integrator : process(nReset, iClk) begin if (nReset
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Datei
CF_SM.vhd
(22); when "11" => leds (3) <= '1'; when others => null; end case; case (data_in_buffer (9 downto 8)) is when "00" => leds (2) <= '0'; when "01" => leds (2) <= blink_counter (25); when "10" => leds (2) <= blink_counter
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Datei
CIC4Stage.vhd
-- 2^16 -- when x"020000" => nShift <= 68; -- 2^17 -- when x"040000" => nShift <= 72; -- 2^18 when others => nShift <= 0; end case; end if; end process Decimation; Integrator : process(nReset, iClk) begin if (nReset
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Datei
HW1Bsp3.vhd
', d => '1', others => '0'); when 3 => return (a => '1', b => '1', g => '1', c => '1', d => '1', others => '0'); when 4 => return (b => '1', c => '1', g => '1', f => '1', others => '0'); when 5 => return (a => '1', f => '1', g => '1', c => '1', d => '1', others => '0'); when 6 => return (a => '1', c => '1', d => '1', e => '1', f => '1', g => '1', others => '0'); when 7 => return (a => '1', b => '1', c => '1', others => '0'); when 8 => return (a => '1', b
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Datei
rechner.vhdl
-------------------- when XODER => ausgabe(15 downto 0) <= wert1(15 downto 0) xor wert2(15 downto 0); ausgabe(19 downto 16) <= "0000"; vorzeichen <= '0'; zustand <= ERG; when others => zustand <= ERROR; end case; when "0100"
in „Process wird kontinuierlich durchloffen - Altium LiveDesign Board“ · FPGA, VHDL & Co. ·
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Datei
sdram_access.vhd
<= '1'; rcas <= '1'; rwe <= '1'; rba <= (others => '0'); radr <= (others => '0'); when CMD_NOP => rcs <= '0'; rras <= '1'; rcas <= '1'; rwe <= '1'; when CMD_ACTIVE => rcs <= '0'; rras <= '0'; rcas <= '1'; rwe <= '1'; rba <= SDRAM_Addr (22 downto
in „Frage zu SDRAM“ · FPGA, VHDL & Co. ·
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Datei
EM4095_Reader.vhd
1'; elsif ((row_parity_error > 1) or (col_parity_error > 1)) then debug_signal(6) <= '1'; end if; when update_output => debug_signal(3 downto 0) <= "1000"; debug_signal(7) <= debug_signal(7) xor '1'; -- LCD aktualisiert when others => debug_signal(3 downto 0) <= "0000"; end case; case state is ------
in „Synthese macht nicht das selbe wie Simulation und "logische" Analyse“ · FPGA, VHDL & Co. ·
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Datei
pseuzufgen3.vhd
B_COUNT + 1; -- Binärzähler wird inkrementiert end if; when "001" => QINT3 <= Q_OUT3; QINT2 <= (others => '0'); QINT4 <= (others => '0'); QINT5 <= (others => '0'); QINT8 <= (others => '0'); QINT16 <= (others => '0'); if QINT3 = "000" then QINT3(0) <= '1' after
in „flexibler Pseudozufallszahlengenerator! was mache ich falsch?“ · FPGA, VHDL & Co. ·
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Datei
Neuron.vhd
others => Add_state <= idle; end case; end if; end process; with Add_Select_a select Add_a <= (others => '0') when "00", Mult_result when "01", (others => '0') when others; with Add_Select_b select Add_b <= (others => '0') when "00", Add_result when "01", (others => '0') when others; Output <= int_Output; Weight_Adr <= Layer_page & Layer_Input_Number; ready <= int_ready and not(execute); error <= Mult_underflow
in „Pipeline MAC-Unit: Problem mit Latency“ · FPGA, VHDL & Co. ·
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Datei
video_generator.vhd
-------- -- horizontal and vertical counters signal hcounter : std_logic_vector(10 downto 0) := (others => '0'); signal vcounter : std_logic_vector(10 downto 0) := (others => '0'); -- active when inside visible screen area. signal video_enable: std_logic; signal blank : std_logic; signal hs : std_logic
in „LVDS Display per Spartan 6 ansteuern“ · FPGA, VHDL & Co. ·
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Datei
i2s_shifter.vhdl
(1); when "11" => bclk <= not bdiv_cnt (2); when others => NULL; end case; end process; process (bclk, res, data, adr, dwen) begin if res = '1' then data_l_temp <= (others => '0'); data_r_temp <= (others => '
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Datei
dap_simple_synth.vhdl
" => siBQ1CofB1S <= signed (siRWValue); when "00111" => siBQ1CofB2S <= signed (siRWValue); when "01000" => siBQ1CofB3S <= signed (siRWValue); when "01001" => siBQ1WrShadow <= '1'; when others => NULL; end case; else case siRReg is when "00000"
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Datei
ether_tx.vhd
<= crc32_n(31 downto 24); tx_en1 <= '1'; when others => data_o1 <= (others => '0'); tx_en1 <= '0'; end case; end if; end process; --calculate crc process (wclk) begin if rising_edge(wclk) then if nibbleout = '1' then if state_txout = pre0 then crc32 <= (others => '1'); elsif state_txout=send then crc32 <= crc(fifo_out, crc32); end if; end if; end if; end process; crc32_n <= not crc32; -- data_o2 <= data_o1 when nibbleout = '1' else "XXXX"& data_o1(7 downto
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Datei
TopAS21.vhd
X"48" => StRcntr1 <= 5; WHEN X"50" => StRcntr1 <= 6; WHEN X"40" =>--keine ref anfahren REF01 <= '1'; StRcntr1 <= 9; WHEN OTHERS => StRcntr1 <= 0; END CASE;--RefBefehl WHEN 2 => --Ausführung RefBefehl:41= X Allein REFRUN2 <= '1'
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Datei
ansteuerung.vhdl
IS WHEN "000000" => rec_cnt<="000001"; WHEN "000001" => rec_cnt<="000010"; WHEN "000010" => rec_cnt<="000011"; WHEN "000011" => rec_cnt<="000100"; WHEN "000100" => rec_cnt<="000101";clk_out_i <= '1'; WHEN "
in „Probleme mit Ansteuerung AD5290“ · Mikrocontroller und Digitale Elektronik ·
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Datei
la_register.vhd
<= to_integer(unsigned(data)); when others => null; end case; when others => null; end case; ------------------------------------------------------------------- -- READ MODE ------------------------------------------------------------
in „Modelsim Problem- bidirektionaler Bus“ · FPGA, VHDL & Co. ·
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Datei
pseuzufgen01.vhd
then -- wenn QINT15 den Wert 000000000000001 hat, wird der Zyklenzähler zurückgesetzt! B_COUNT <= (others => '0'); else B_COUNT <= B_COUNT + 1; -- gibt an nach wie viel Taktzyklen sich die Periode wiederholt !!! end if; end if; when others => if QINT16 = "0000000000000000" then -- wenn alle Registerausgänge
in „flexibler Pseudozufallszahlengenerator! was mache ich falsch?“ · FPGA, VHDL & Co. ·
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Datei
pseuzufgen01.vhd
then -- wenn QINT15 den Wert 000000000000001 hat, wird der Zyklenzähler zurückgesetzt! B_COUNT <= (others => '0'); else B_COUNT <= B_COUNT + 1; -- gibt an nach wie viel Taktzyklen sich die Periode wiederholt !!! end if; end if; when others => if QINT16 = "0000000000000000" then -- wenn alle Registerausgänge
in „Fehlermeldung ISE: Can not determine the "others" values in aggregate ?“ · FPGA, VHDL & Co. ·
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Datei
BCDto7SegmentDecoder.vhd
, 3 => ledOff, 4=> ledOff, others => ledOn) when "0100", (1 => ledOff, 4=> ledOff, others => ledOn) when "0101", (1 => ledOff, others => ledOn) when "0110", (0 => ledOn, 1 => ledOn, 2 => ledOn, others => ledOff) when "0111", (others => ledOn) when "1000", (4 => ledOff,others => ledOn) when "1001", (others => ledOff) when others; end RTL;
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Datei
Main.vhd
implementierte, sekundenweise Ausgabe TEST <= '1'; DEZIMALZIFFERN <= to_bcd(UMDREHUNGEN); UMDREHUNGEN <= (others => '0'); else TEST <= '0'; end if; end if; end process UMDREHUNGEN_DETECT; -- Sieben Segment Codierer SEVEN_SEG: process(LED) begin case LED is when X"0" => SEG_OUT <= "0000001"; --0 when X"1" => SEG_OUT
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Datei
Noise_Shaper.vhd
LT2_old <= (others => '0'); LT3_old <= (others => '0'); LT4_old <= (others => '0'); else case state_reg is when 0 => if(new_data = '1') then state_reg <= 1; MAC_exec <= '0'; MAC_preload <= '0'; program_counter <= 0;
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Datei
dmcache.vhd
cacheLines(to_integer(unsigned(req_line))); with req_word select temp_data <= temp_line(15 downto 0) when "00", temp_line(31 downto 16) when "01", temp_line(47 downto 32) when "10", temp_line(63 downto 48) when others; isvalid <= valid(to_integer(unsigned(req_line))); process begin if (reset = '1') then
in „cachemodul, Simulation ok, aber auch bereit für die Synthese?“ · FPGA, VHDL & Co. ·
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Datei
Main.vhd
; else F_ZUSTAND <= GO; end if; when NEWHIGHSCORE => LCD_SEL <= 5; EN_WR_SCORE_REG <= '1'; when others => LCD_SEL <= 1; end case; end process FSM; LCD_MUSTER: process(LCD_SEL, POS1, POS2, POS3, POS4, ASK_VALUE, HEX_POS1, HEX_POS2) begin
in „[VHDL] Komponenten Einbinden und wegoptimieren von Signalen verhindern“ · FPGA, VHDL & Co. ·
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Datei
LCD-Componenten.txt
done => state <= idle; end case; end if; end process; with state select write_done <= '1' when done, '0' when others; with state select lcd_e_w <= '1' when s2|s6, '0' when others; with state select lcd_rw <= '1' when idle|s4|s8|done, '0' when others; with state select lcd_db_w <= db(7 downto
in „LCD Ansteuerung mit spartan-3E starter“ · FPGA, VHDL & Co. ·
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Datei
SweepGen.vhd
_Process : process(CLK200) begin if rising_edge(CLK200) then if Reset = '0' then DelayOBUFIn <= (others=>'0'); BitCount <= 0; LED <= '1'; STATE <= SetCalibration; else LED <= '0'; case STATE is when SetCalibration => --PLL Locked? if Locked_i = '1' then STATE <= DoCalibration; end if; when DoCalibration => STATE <= CalibrationDone; when CalibrationDone => DelayOBUFIn <= (others=>'0'); if ClkCount = 5 then ClkCount <= 0; STATE <= SetData; else ClkCount <= ClkCount + 1; end if; when SetData => if MuxOSel = 15 and BitCount = 7 then MuxOSel
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Datei
adcamp01.vhd
x"2B", init(0) when x"2C", init(0) when x"2D", init(0) when x"2E", init(0) when x"2F", '0' when others; with counter3 select ad_conv <= '1' when x"01", '0' when others; --zum testen with counter3 select ad_conv2 <= '1'
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Datei
main.vhd
when ADDR_MUX_HM2 ='1' else (others => 'Z'); -- Treiber Datenbus -- DATA <= DATA_BUF when ADDR(3) ='0' else (others => 'Z'); -- Schreiben process begin wait until falling_edge(NWE); if (NE1='1') then NULL
in „Erzeugung von Tri - State Signalen?“ · FPGA, VHDL & Co. ·
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Datei
MCU.vhd
"; FSMState <= Idle; BusWE <= '1'; RamCS <= '1'; BusAdress <= (Others => '0'); RamInitHappend <= '1'; RamCLKce <= '1'; end if; when Idle => State(3 downto 0) <= "0100"; case Sel is when "0000" => FSMState <= Idle; Bussy <= '0'; when "0001" => FSMState <= RamRead0; Bussy
in „Problem mit der Ansteuerung von PSRAM“ · FPGA, VHDL & Co. ·
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Datei
MCU.vhd
"; FSMState <= Idle; BusWE <= '1'; RamCS <= '1'; BusAdress <= (Others => '0'); RamInitHappend <= '1'; RamCLKce <= '1'; end if; when Idle => State(3 downto 0) <= "0100"; case Sel is when "0000" => FSMState <= Idle; Bussy <= '0'; when "0001" => FSMState <= RamRead0; Bussy
in „Problem mit der Ansteuerung von PSRAM“ · FPGA, VHDL & Co. ·
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Datei
FCrypt.vhd
generate_key : process (clock) variable n, m : byte; begin if rising_edge(clock) then case state is when zero => -- Initialisierungsphase -- Output-Ports ready <= '0'; done <= '0'; input <= '0'; output <= '0'; outkey_byte <= (others => '0'); -- Inkey write_enable_inkey <= '0'; address_inkey <= (others
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Datei
SDRAM_Controller.vhd
phase, then is used to trigger refreshes. constant startup_refresh_max : unsigned(13 downto 0) := (others => '1'); signal startup_refresh_count : unsigned(13 downto 0) := startup_refresh_max-to_unsigned(sdram_startup_cycles,14); -- logic to decide when to refresh signal pending_refresh : std_logic := '
in „XC6SLX16 Spartan 6 Entwicklungsboard“ · FPGA, VHDL & Co. ·
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Datei
top.vhd
allbit(38-send_databit_cnt); when 2 => MO_reg <= allbit(30-send_databit_cnt); when 3 => MO_reg <= allbit(22-send_databit_cnt); when others => end case; if send_databit_cnt < 6 then send_databit_cnt <= send_databit_cnt + 1; elsif send_databit_cnt
in „INOUT wird bei der Synthese zu OUTPUT konvertiert“ · FPGA, VHDL & Co. ·
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Datei
IIR_Statemachine.vhd
(others => '0'); nA1 <= (others => '0'); nA2 <= (others => '0'); nX <= (others => '0'); nY <= (others => '0'); oDone <= '0'; oIIR_TX <= (others => '0'); else case state is when idle => oDone <= '0'; if(iNewValue
in „IIR Filter 2. Ordnung in FPGA implementieren“ · Digitale Signalverarbeitung / DSP / Machine Learning ·
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PDF
rts18160128fhc04-P16885-X01.pdf
active. 18 RESB This is a reset signal input. Low active. D/C=”H”: Data. 19 DC D/C=”L”: Command. When connected to 8080-series MPU. WR pin. When RW =”L”: Write signal input. 20 RW When connected to 6800-series MPU. When RW =”H”: Read. When RW =”L”: Write. When connected to 8080-series MPU. RD pin.When
in „RitDisplay RTS18160128FHC04 P16885 1,8" OLED Touch STM8“ · Mikrocontroller und Digitale Elektronik ·
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Datei
Main.vhd
; end if; else FSM_F_ZUSTAND <= FSM_RESET; end if; when FSM_WAIT_PRESENCE => READ_EN <= '1'; -- Read Slot auslösen if INPUT_BUFFER /= "1111111111111111" then -- prüfen, ob eine Null gelesen wurde FSM_F_ZUSTAND <= FSM_SKIP_ROM; --INPUT_BUFFER <= (others =
in „[Fehlersuche] Ansteuerung eines 1-Wire Sensors“ · FPGA, VHDL & Co. ·
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Datei
top.vhdl
to_unsigned(x mod 64)); ramp2 := std_logic_vector(to_unsigned((XMAX - x) mod 64)); case section is when 0|3|4|6|7|10|11|13|14 => r <= ramp1; when 8|9|12 => r <= (others => '1'); when others => r <= (others => '0'); end case; case section is when 1|3|5|6|8|10|12 => g <= ramp1; when 13 => g <= ramp2; when 7|9|11 => g <= (others => '1'); when others => g <= (others => '0'); end case; case section is when 2|4|5|6|9|11|12 => b <= ramp1; when 14 => b <= ramp2; when 7|8|10 => b <= (others => '1'); when others => b <= (others =
in „Anschluß TFT-LCD-Modul SHARP LQ092B5DW01 Pollin“ · Mikrocontroller und Digitale Elektronik ·
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Datei
IIR.vhd
(others => '0'); nA1 <= (others => '0'); nA2 <= (others => '0'); nX <= (others => '0'); oDone <= '0'; oIIR_TX <= (others => '0'); else case state is when idle => oDone <= '0'; if(iNewValue = '1') then -- If
in „IIR Filter 2. Ordnung in FPGA implementieren“ · Digitale Signalverarbeitung / DSP / Machine Learning ·
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Datei
CONTROLLER.vhd
nach dem nächsten Takt abgeschaltet PORT0_MODUS <= UNUSED; -- und Port 0 wird freigegeben end if; when Z2 => -- Zustand 2 SM2 <= Z1; PORT0_E <= '0'; -- Datenausgabe an Port 0 abschalten PORT0_DO <= (others => '0'); -- Port 0 Datenausgabe löschen when others => -- anderer Zustand SM2 <= Z1; end case;
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Datei
IIR.vhd
(others => '0'); nA1 <= (others => '0'); nA2 <= (others => '0'); nX <= (others => '0'); nY <= (others => '0'); oDone <= '0'; oIIR_TX <= (others => '0'); else case state is when idle => oDone <= '0'; if(iNewValue
in „IIR Filter 2. Ordnung in FPGA implementieren“ · Digitale Signalverarbeitung / DSP / Machine Learning ·
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Datei
Main.vhd
; end if; else FSM_F_ZUSTAND <= FSM_RESET; end if; when FSM_WAIT_PRESENCE => READ_EN <= '1'; -- Read Slot auslösen if INPUT_BUFFER /= "1111111111111111" then -- prüfen, ob eine Null gelesen wurde FSM_F_ZUSTAND <= FSM_SKIP_ROM; --INPUT_BUFFER <= (others =
in „[Fehlersuche] Ansteuerung eines 1-Wire Sensors“ · FPGA, VHDL & Co. ·