openocd AT91SAM9260

Konfiguration
Linux: opensuse 11.0
Jtagger: ARM-USB-OCD von Olimex
Board: spezial mit AT91SAM9260

Das erste was auffällt; wenn openocd gestartet wird, dann kommt schon 
ein Fehler.
Bei dem Befehl Reset wird die CPU auch geresetet, kann aber nicht im 
halt verweilen. Dann gibt es immer ein Timing. Manchmal funktioniert es 
doch, eben nicht sichern.
Hat jemand eine Idee welchen Parameter ich falsch habe?



x1-6-00-1d-92-05-7d-7a:/home/red/trunk/src # ./openocd -f sam9.cfg
Open On-Chip Debugger 1.0 (2009-04-09-10:49) svn:1454


BUGS? Read http://svn.berlios.de/svnroot/repos/openocd/trunk/BUGS


$URL: http://svn.berlios.de/svnroot/repos/openocd/trunk/src/openocd.c $
jtag_speed: 3
     TapName            | Enabled |   IdCode      Expected    IrLen 
IrCap  IrMask Instr
---|--------------------|---------|------------|------------|------|---- 
--|------|---------
 0 | at91sam9260.cpu    |    Y    | 0x00000000 | 0x0792603f | 0x04 | 
0x01 | 0x0f | 0x0f
Error: JTAG communication failure, check connection, JTAG interface, 
target power etc.
Error: trying to validate configured JTAG chain anyway...
Error: Could not validate JTAG scan chain, IR mismatch, scan returned 
0x00. tap=at91sam9260.cpu pos=0 expected 0x1 got 0
Warn : Could not validate JTAG chain, continuing anyway...
Warn : TAP at91sam9260.cpu:
Warn : value captured during scan didn't pass the requested check:
Warn : captured: 0x00 check_value: 0x01 check_mask: 0x0F
Warn : in_handler: w/o "in_value", mismatch in SIR
Warn : TAP at91sam9260.cpu:
Warn : value captured during scan didn't pass the requested check:
Warn : captured: 0x00 check_value: 0x01 check_mask: 0x0F
Warn : in_handler: w/o "in_value", mismatch in SIR
Warn : no tcl port specified, using default port 6666
Info : accepting 'telnet' connection from 0
Error: Target not examined yet
Runtime error, file "command.c", line 456:
    Info : JTAG tap: at91sam9260.cpu tap/device found: 0x0792603f 
(Manufacturer: 0x01f, Part: 0x7926, Version: 0x0)
Info : JTAG Tap/device matched
8 kHz
Error: timed out while waiting for target halted
Runtime error, file "sam9.cfg", line 79:


red@x1-6-00-1d-92-05-7d-7a:~> telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> reset
JTAG tap: at91sam9260.cpu tap/device found: 0x0792603f (Manufacturer: 
0x01f, Part: 0x7926, Version: 0x0)
JTAG Tap/device matched
8 kHz
target state: halted
target halted in ARM state due to debug-request, current mode: 
Supervisor
cpsr: 0x400000d3 pc: 0x00000500
MMU: disabled, D-Cache: disabled, I-Cache: enabled
6000 kHz
dcc downloads are enabled
flash 'cfi' found at 0x10000000

> mdw 0x10000000
0x10000000: ea000015

> Connection closed by foreign host.
red@x1-6-00-1d-92-05-7d-7a:~> telnet localhost 4444
Trying 127.0.0.1...
Connected to localhost.
Escape character is '^]'.
Open On-Chip Debugger
> halt
Target not examined yet
Runtime error, file "command.c", line 456:

> reset
JTAG tap: at91sam9260.cpu tap/device found: 0x0792603f (Manufacturer: 
0x01f, Part: 0x7926, Version: 0x0)
JTAG Tap/device matched
8 kHz
timed out while waiting for target halted
Runtime error, file "sam9.cfg", line 79:

in procedure 'at91sam_init' called at file "sam9.cfg", line 0

>

sam9.cfg :



 #daemon configuration
 telnet_port 4444
 gdb_port 8888


 # home-made jtag-interface

 interface ft2232
 ft2232_device_desc "Olimex OpenOCD JTAG A"
 ft2232_layout olimex-jtag
 ft2232_vid_pid 0x15ba 0x0003
# ft2232_latency 2

jtag_speed 3



######################################
# Target:    Atmel AT91SAM9260
######################################

if { [info exists CHIPNAME] } {
   set  _CHIPNAME $CHIPNAME
} else {
   set  _CHIPNAME at91sam9260
}

if { [info exists ENDIAN] } {
   set  _ENDIAN $ENDIAN
} else {
   set  _ENDIAN little
}

if { [info exists CPUTAPID ] } {
   set _CPUTAPID $CPUTAPID
} else {
  # force an error till we get a good number
   set _CPUTAPID 0x0792603f
}


reset_config trst_and_srst


jtag_nsrst_delay 200
jtag_ntrst_delay 200


jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf 
-expected-id $_CPUTAPID


######################
# Target configuration
######################

set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position 
$_TARGETNAME -variant arm926ejs

$_TARGETNAME invoke-event halted

# Internal sram1 memory
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 
-work-area-size 0x1000 -work-area-backup 1

scan_chain
$_TARGETNAME configure -event reset-deassert-post {at91sam_init}


# Flash configuration
#flash bank cfi <base> <size> <chip width> <bus width> <target#>
flash bank cfi 0x10000000 0x01000000 2 2 $_TARGETNAME


proc at91sam_init { } {

  # at reset chip runs at 32khz
  jtag_khz 8
  mww 0xfffffd08 0xa5000501         # RSTC_MR : enable user reset
  mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog

  mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main 
oscillator
  sleep 20                          # wait 20 ms
  mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main 
oscillator
  sleep 10                          # wait 10 ms
  mww 0xfffffc28 0x2060bf09         # CKGR_PLLAR: Set PLLA Register for 
198,656MHz
  sleep 20                          # wait 20 ms
  mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler
  sleep 10                          # wait 10 ms
  mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is 
selected
  sleep 10                          # wait 10 ms

  # Now run at anything fast... ie: 10mhz!
  jtag_khz 10000                    # Increase JTAG Speed to 6 MHz
  arm7_9 dcc_downloads enable       # Enable faster DCC downloads

  mww 0xffffec00 0x0a0a0a0a         # SMC_SETUP0 : Setup SMC for Intel 
NOR Flash JS28F128P30T85 128MBit
  mww 0xffffec04 0x0b0b0b0b         # SMC_PULSE0
  mww 0xffffec08 0x00160016         # SMC_CYCLE0
  mww 0xffffec0c 0x00161003         # SMC_MODE0

  flash probe 0                     # Identify flash bank 0

  mww 0xfffff870 0xffff0000         # PIO_ASR : Select peripheral 
function for D15..D31
  mww 0xfffff804 0xffff0000         # PIO_PDR : Disable PIO function for 
D15..D31

  mww 0xffffef1c 0x2                # EBI_CSA : Assign EBI Chip Select 1 
to SDRAM

  mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x 
Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
  #mww 0xffffea08 0x85227254         # SDRAMC_CR : Configure SDRAM (2 x 
Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)

  mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
  mww 0x20000000 0
  mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks 
Precharge' command
  mww 0x20000000 0
  mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 
'Auto-Refresh' Command
  mww 0x20000000 0
  mww 0xffffea00 0x4
  mww 0x20000000 0
  mww 0xffffea00 0x4
  mww 0x20000000 0
  mww 0xffffea00 0x4
  mww 0x20000000 0
  mww 0xffffea00 0x4
  mww 0x20000000 0
  mww 0xffffea00 0x4
  mww 0x20000000 0
  mww 0xffffea00 0x4
  mww 0x20000000 0
  mww 0xffffea00 0x4
  mww 0x20000000 0
  mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode 
Register' command
  mww 0x20000000 0
  mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
  mww 0x20000000 0
  mww 0xffffea04 0x5d2              # SDRAMC_TR : Set refresh timer 
count to 15us
}



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