1 | library IEEE;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.std_logic_arith.all;
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4 |
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5 | entity spi is
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6 | port ( spi_Tx : out std_logic; -- SPI-lines
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7 | spi_clk : out std_logic;
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8 | spi_cs : out std_logic;
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9 | spi_Rx : in std_logic;
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10 |
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11 | new_data : in std_logic; -- sign
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12 |
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13 | TxData : in std_logic_vector(7 downto 0);
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14 | RxData : out std_logic_vector(7 downto 0);
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15 |
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16 | reset : in std_logic;
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17 | clk : in std_logic);
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18 | end spi;
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19 |
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20 | -------------------------------------------------------------------------------
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21 | -- ARCHITECTURE
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22 | -------------------------------------------------------------------------------
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23 | architecture rtl of spi is
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24 |
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25 | signal s_TxBuf : std_logic_vector(7 downto 0);
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26 | signal s_RxBuf : std_logic_vector(7 downto 0);
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27 | signal s_cnt : std_logic_vector(4 downto 0);
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28 | signal s_busy : std_logic;
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29 |
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30 | begin
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31 |
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32 | p_spi_master : process(clk,reset)
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33 | begin
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34 | if(reset = '1')then
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35 | s_TxBuf <= (others => '0');
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36 | s_RxBuf <= (others => '0');
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37 | s_cnt <= (others => '0');
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38 | s_busy <= '0';
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39 | spi_cs <= '1';
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40 | spi_clk <= '1';
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41 | spi_Tx <= '1';
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42 | elsif(clk = '1' and clk'event) then
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43 | if(new_data = '1' and s_busy = '0')then
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44 | s_TxBuf <= TxData;
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45 | s_busy <= '1';
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46 | s_cnt <= (others => '0');
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47 | spi_cs <= '0';
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48 | end if;
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49 |
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50 | if(s_busy = '1')then -- shifting is enabled
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51 | s_cnt <= unsigned(s_cnt) + conv_unsigned(1,1);
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52 | if(s_cnt(4) /= '1')then -- are 16 ticks over?
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53 | if(s_cnt(0) = '0')then -- shift out data on every "even" LSB
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54 | s_TxBuf <= s_TxBuf(6 downto 0) & '0'; -- shift operation
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55 | spi_Tx <= s_TxBuf(7); -- data out
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56 | spi_clk <= '0'; -- toggle sclk
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57 | else -- s_cnt is "odd": rising sclk
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58 | s_RxBuf <= s_RxBuf(6 downto 0) & spi_Rx; -- read RxLine
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59 | spi_clk <= '1';
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60 | end if;
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61 | else -- 16th tick is reached
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62 | -- bring module in 'idle'-state
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63 | s_busy <= '0';
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64 | spi_cs <= '1';
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65 | spi_Tx <= '1';
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66 | spi_clk <= '1';
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67 | RxData <= s_RxBuf;
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68 | s_TxBuf <= (others => '0');
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69 | s_RxBuf <= (others => '0');
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70 | s_cnt <= (others => '0');
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71 | end if;
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72 | end if;
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73 | end if;
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74 | end process p_spi_master;
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75 | end rtl;
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