Fragen zum IDDR beim Virtex 5

Library UNISIM;

use UNISIM.vcomponents.all;

--  <-----Cut code below this line and paste into the architecture body---->

   -- IDDR: Double Data Rate Input Register with Set, Reset

   --       and Clock Enable. 

   --       Virtex-5

   -- Xilinx HDL Language Template, version 13.4

   IDDR_inst : IDDR 

   generic map (

      DDR_CLK_EDGE => "OPPOSITE_EDGE", -- "OPPOSITE_EDGE", "SAME_EDGE" 

                                       -- or "SAME_EDGE_PIPELINED" 

      INIT_Q1 => '0', -- Initial value of Q1: '0' or '1'

      INIT_Q2 => '0', -- Initial value of Q2: '0' or '1'

      SRTYPE => "SYNC") -- Set/Reset type: "SYNC" or "ASYNC" 

   port map (

      Q1 => Q1, -- 1-bit output for positive edge of clock 

      Q2 => Q2, -- 1-bit output for negative edge of clock

      C => C,   -- 1-bit clock input

      CE => CE, -- 1-bit clock enable input

      D => D,   -- 1-bit DDR data input

      R => R,   -- 1-bit reset

      S => S    -- 1-bit set

      );

   -- End of IDDR_inst instantiation

Virtex-5 devices have dedicated registers in the ILOGIC to implement input double-datarate

(DDR) registers. This feature is used by instantiating the IDDR primitive.

There is only one clock input to the IDDR primitive. Falling edge data is clocked by a

locally inverted version of the input clock. All clocks feeding into the I/O tile are fully

multiplexed, i.e., there is no clock sharing between ILOGIC and OLOGIC blocks.