Xmega128-a1-explained und ASF

// Sollte vorne zu den anderen includes

#include <ebi.h>

#include <ebi_port.h>

#include <hugemem.h>

// constants for refresh and init

//! SDRAM initialization delay in number of CLKper2 cycles (100 us)

#define BOARD_EBI_SDRAM_INITDLY         \

  (100 * 2 * sysclk_get_per2_hz() / 1000000)

//! SDRAM refresh interval in number of CLKper2 cycles (16 us)

#define BOARD_EBI_SDRAM_REFRESH         \

  (16 * 2 * sysclk_get_per2_hz() / 1000000)

/**

 * \brief EBI chip select configuration

 *

 * This struct holds the configuration for the chip select used to set up the

 * SDRAM. The example code will use the EBI helper function to setup the

 * contents before writing the configuration using ebi_cs_write_config().

 */

static struct ebi_cs_config     cs_config;

/**

 * \brief EBI SDRAM configuration

 *

 * This struct holds the configuration for the SDRAM.  The example code will

 * use the EBI helper function to setup the contents before writing the

 * configuration using ebi_sdram_write_config().

 */

static struct ebi_sdram_config  sdram_config;

// Init the EBI and the RAM. Note that the RAM will not be cleared here. 

static void InitSDRAM(void) {

  /*

   * Configure the EBI port with 12 address lines, no address latches or

   * low pin count, and set it in SDRAM mode with 3-port EBI port.

   */

  ebi_setup_port(12, 0, 0, EBI_PORT_3PORT | EBI_PORT_SDRAM);

  /*

   * Configure the EBI chip select for an 8 MB SDRAM located at

   * \ref BOARD_EBI_SDRAM_BASE.

   */

  ebi_cs_set_mode(&cs_config, EBI_CS_MODE_SDRAM_gc);

  ebi_cs_set_address_size(&cs_config, EBI_CS_ASIZE_8MB_gc);

  ebi_cs_set_base_address(&cs_config, BOARD_EBI_SDRAM_BASE);

  /* Configure the EBI chip select to be in SDRAM mode. */

  ebi_sdram_set_mode(&cs_config, EBI_CS_SDMODE_NORMAL_gc);

  /* Setup the number of SDRAM rows and columns. */

  ebi_sdram_set_row_bits(&sdram_config, 12);

  ebi_sdram_set_col_bits(&sdram_config, 10);

  /* Further, setup the SDRAM timing. */

  ebi_sdram_set_cas_latency(&sdram_config, 3);

  ebi_sdram_set_mode_delay(&sdram_config, EBI_MRDLY_2CLK_gc);

  ebi_sdram_set_row_cycle_delay(&sdram_config, EBI_ROWCYCDLY_7CLK_gc);

  ebi_sdram_set_row_to_precharge_delay(&sdram_config, EBI_RPDLY_7CLK_gc);

  ebi_sdram_set_write_recovery_delay(&sdram_config, EBI_WRDLY_1CLK_gc);

  ebi_sdram_set_self_refresh_to_active_delay(&sdram_config,

      EBI_ESRDLY_7CLK_gc);

  ebi_sdram_set_row_to_col_delay(&sdram_config, EBI_ROWCOLDLY_7CLK_gc);

  ebi_sdram_set_refresh_period(&sdram_config, BOARD_EBI_SDRAM_REFRESH);

  ebi_sdram_set_initialization_delay(&sdram_config,

      BOARD_EBI_SDRAM_INITDLY);

  /* Write SDRAM configuration into the EBI registers. */

  ebi_sdram_write_config(&sdram_config);

  /* Write the chip select configuration into the EBI registers. */

  ebi_cs_write_config(EBI_SDRAM_CS, &cs_config);

  ebi_enable_cs(EBI_SDRAM_CS, &cs_config);

  do {

    // Wait for SDRAM to initialize.

  } while (!ebi_sdram_is_ready());

  /* Debug: Enable LED1: SDRAM is ready. */

  LED_PORT.OUTCLR = OLED1;

    _delay_ms(100);

  LED_PORT.OUTSET = OLED1;

}

// Clear and Write SDRam

static void ClearSDRAM(void) {

  hugemem_ptr_t n;

  for (n = BOARD_EBI_SDRAM_BASE; n < (BOARD_EBI_SDRAM_SIZE + BOARD_EBI_SDRAM_BASE);n+=4) {

    hugemem_write32(n,0);

  }

}

// My application specific write routine, writeptr is a global , as is the time variables 'days, hours, minutes, seconds'

static void WriteSet(uint16_t x, uint16_t y , uint16_t z){

uint32_t time = ((days * 16777216) + (hours * 65536) + (minutes * 256) + seconds);

// Wrap around pointer if its beyond the RAM Range

  if (writeptr > (BOARD_EBI_SDRAM_SIZE + BOARD_EBI_SDRAM_BASE)) writeptr = BOARD_EBI_SDRAM_BASE;

  hugemem_write32(writeptr ,time);

  writeptr +=4;

  hugemem_write16(writeptr ,x);

  writeptr +=2;

  hugemem_write16(writeptr ,y);

  writeptr +=2;

  hugemem_write16(writeptr ,z);

  writeptr +=2;

}