Guten Tag,
Ich sitze im Moment an einem Problem und weiß nicht wirklich woher es
kommt.
Also, was möchte ich beschreiben:
Einen Eingangsmultiplexer, welcher mit IN_MODE das interne Signal
auswählt und einen Ausgangsmultiplexer, welcher mittels OUT_MODE das
interne Signal auf verschiedene Ausgänge aufteilen kann.
Was wird draus:
Anstelle des Ausgangsmultiplexers werden zwei 8 bit lachtes erzeugt.
Hier mein Code:
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 |
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4 | entity Instruction_Ex is
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5 | Port ( CLK : in std_logic;
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6 | INPUT_ALU : in std_logic_vector (7 downto 0);
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7 | INPUT_BYP : in std_logic_vector(7 downto 0);
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8 | INPUT_MODE : in std_logic_vector (1 downto 0);
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9 | OUTPUT_MODE : in std_logic_vector (1 downto 0);
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10 | OUTPUT_REG : out std_logic_vector (7 downto 0);
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11 | OUTPUT_DIRECT : out std_logic_vector (7 downto 0));
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12 | end Instruction_Ex;
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13 |
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14 | architecture Behavioral of Instruction_Ex is
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15 |
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16 | signal output_int : std_logic_vector(7 downto 0);
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17 | signal input_int : std_logic_vector (7 downto 0);
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18 |
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19 | begin
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20 |
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21 | INPUTMux:process(INPUT_MODE,INPUT_ALU,INPUT_BYP)
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22 | begin
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23 | case INPUT_MODE is
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24 | when "00" =>
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25 | input_int <= INPUT_ALU;
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26 | when "01" =>
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27 | input_int <= INPUT_BYP;
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28 | when others =>
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29 | input_int <= INPUT_ALU;
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30 | end case;
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31 | end process;
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32 |
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33 | OUTPUTMux:process(OUTPUT_MODE,input_int,INPUT_ALU,INPUT_BYP,INPUT_MODE)
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34 | begin
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35 | case OUTPUT_MODE is
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36 | when "00" =>
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37 | OUTPUT_REG <= input_int;
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38 | when "01" =>
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39 | OUTPUT_DIRECT <= input_int;
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40 | when others =>
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41 | OUTPUT_REG <= input_int;
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42 | end case;
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43 | end process;
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44 |
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45 | end Behavioral;
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