Hallo, ich habe mal ein kleines SPI- Modul im Internet gefunden und
leider funktioniert dieses nicht so wie es sollte. Könnte bitte jemand
drüberschauen und mir sagen wo da der Fehler ? :) -Danke
Wenn möglich würde ich es super finden wenn ihr mir den Code auch näher
erläutert denn zu 100% verstehe ich ihn nicht.
1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.numeric_std.all;
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4 |
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5 | entity spi is
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6 | Generic (Width : integer := 8);
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7 | Port ( Clk_i : in STD_LOGIC;
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8 | Reset_n_i : in STD_LOGIC;
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9 | Data_i : in STD_LOGIC_vector(Width-1 downto 0);
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10 | SClk_o : out STD_LOGIC;
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11 | MOSI_o : out STD_LOGIC;
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12 | MISO_i : in STD_LOGIC;
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13 | SS_o : out STD_LOGIC;
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14 | Ready_i : in STD_LOGIC);
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15 | end spi;
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16 |
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17 | architecture rtl of spi is
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18 |
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19 | type States is (Idle, Data_transfer, Stop);
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20 | signal State: States := Idle;
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21 | signal Tx_reg : unsigned(Width-1 downto 0);
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22 | signal Count: unsigned(Width-1 downto 0);
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23 |
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24 | begin
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25 |
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26 | MOSI_o <= Tx_reg(Tx_reg'left); -- Data from Master to Slave
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27 | SCLK_o <= Clk_i; -- Master Clk_i send to SCLK
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28 |
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29 | spi : process(Clk_i,Reset_n_i)
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30 | begin
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31 | if Reset_n_i = '0' then
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32 | Count <= (others => '0'); -- Init Data bit counter
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33 | State <= Idle;
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34 | Tx_reg <= unsigned(Data_i); -- Load parallel data
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35 | SS_o <= '1'; -- Deselect Slave
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36 | elsif rising_edge(Clk_i) then
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37 | case State is
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38 | when Idle =>
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39 | if Ready_i = '1' then
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40 | SS_o <= '0'; -- Select Slave aktive
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41 | State <= Data_Transfer; -- Change state
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42 | else
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43 | State <= Idle;
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44 | end if;
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45 | when Data_transfer =>
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46 | if Count < (Width-1) then
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47 | Count <= Count+1;
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48 | Tx_reg <= Tx_reg(Tx_reg'left-1 downto 0)& MISO_i;
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49 | else
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50 | State <= Stop; -- Change state
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51 | end if;
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52 | when Stop =>
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53 | SS_o <= '1'; -- Deselect slave
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54 | end case;
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55 | end if;
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56 | end process;
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57 | end rtl;
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