[xmega128a1] SPI Slave DMA RX TX

ISR (PORTA_INT0_vect) // Sync with SS-Pin

{

  DMA.CH0.CTRLA |= (1<<DMA_CH_ENABLE_bp);

}

int main(void)

{

  // init SPI

  PORTC.DIR = 0x41;

  SPIC.CTRL = (0<<SPI_CLK2X_bp)

            | (1<<SPI_ENABLE_bp)

        | (0<<SPI_DORD_bp)

        | (0<<SPI_MASTER_bp)

        | SPI_MODE_0_gc;

  SPIC.INTCTRL = SPI_INTLVL_OFF_gc;

  // init DMA Controller

  DMA.CH0.TRIGSRC = DMA_CH_TRIGSRC_SPIC_gc;

  DMA.CH0.TRFCNT = 2048;    // Data length

  DMA.CH0.REPCNT = 0;

  DMA.CH0.SRCADDR0  = (((uint16_t) &SPIC.DATA) >> 0*8) & 0xff;

  DMA.CH0.SRCADDR1  = (((uint16_t) &SPIC.DATA) >> 1*8) & 0xFF;

  DMA.CH0.SRCADDR2  = 0;

  DMA.CH0.DESTADDR0 = (((uint16_t) Rx_Buf) >> 0*8) & 0xff;

  DMA.CH0.DESTADDR1 = (((uint16_t) Rx_Buf) >> 1*8) & 0xFF;

  DMA.CH0.DESTADDR2 = 0;

  DMA.CH0.ADDRCTRL = DMA_CH_SRCRELOAD_NONE_gc

                   | DMA_CH_SRCDIR_FIXED_gc

           | DMA_CH_DESTRELOAD_TRANSACTION_gc

           | DMA_CH_DESTDIR_INC_gc;

  DMA.CH0.CTRLB = DMA_CH_ERRINTLVL_OFF_gc

                | DMA_CH_TRNINTLVL_HI_gc;

  DMA.CH0.CTRLA = (1<<DMA_CH_ENABLE_bp)

                | (0<<DMA_CH_RESET_bp)

          | (0<<DMA_CH_REPEAT_bp)

          | (0<<DMA_CH_TRFREQ_bp)

          | (1<<DMA_CH_SINGLE_bp)

          | DMA_CH_BURSTLEN_1BYTE_gc;

  DMA.CTRL = (1<<DMA_CH_ENABLE_bp)

           | (0<<DMA_CH_RESET_bp)

       | (0<<DMA_DBUFMODE_gp)

       | (0<<DMA_PRIMODE_gp);

PORTA.INT0MASK = PIN4_bm;

PORTA.PIN4CTRL = PORT_OPC_WIREDANDPULL_gc | PORT_ISC_FALLING_gc;

PORTA.INTCTRL |= PORT_INT0LVL_HI_gc;

PMIC.CTRL |= PMIC_HILVLEN_bm | PMIC_MEDLVLEN_bm | PMIC_LOLVLEN_bm;    

sei();

while(1)

 {

 .......

 }

}

ISR( DMA_CH0_vect)

{

  DMA.INTFLAGS |= (1<<DMA_CH0TRNIF_bp);

  //DMA.CH0.CTRLA |= (1<<DMA_CH_ENABLE_bp);

  PORTC.OUTTGL = 0x01;

}