VHDL - Syntaxerror in Case-When-Anweisung

Der Ausdruck darf nur in einem Prozess verwendet werden.

Probier mal das hier:

1

WITH sw SELECT

2

    seg <= "1111110" WHEN "0000",

3

                 'X' WHEN OTHERS;

Mit with select wirds auch nicht besser, ich bekomme 32 mal die 
Fehlermeldung:
Type of seg is incompatible with type of <=.

entity BCDDec is
port (sw : in std_logic_vector(3 downto 0);
    seg: out std_logic_vector(6 downto 0));
end BCDDec;

architecture Behavioral of BCDDec is
begin
  with sw select
    seg <= "1111110" when "0000",
    seg <= "0110000" when "0001",
    seg <= "1101101" when "0010",
    seg <= "1111001" when "0011",
    seg <= "0110011" when "0100",
    seg <= "1011010" when "0101",
    seg <= "0111101" when "0110",
    seg <= "1110000" when "0111",
    seg <= "1111110" when "1000",
    seg <= "1111011" when "1001",
    seg <= "1110111" when "1010",
    seg <= "1111111" when "1011",
    seg <= "1001111" when "1100",
    seg <= "1111110" when "1101",
    seg <= "1001111" when "1110",
    seg <= "1000111" when "1111",
    seg <= "0000000" WHEN OTHERS;
end Behavioral;

In der case-Variante schreibt er "Syntax error near "case"."

so ist es richtig

  with sw select
    seg <= "1111110" when "0000",
           "1001110" when "0001",
           "0000000" WHEN OTHERS;

hast du die libs eingebunden?

1

library ieee;

2

use ieee.std_logic_1164.all;

Eine case Anweisung gehört immer in einen process, da sequentielle 
Anweisung.

Der Besucher

Oh, hatte lulu ja schon geschrieben. Habs übersehen.