spartan6 bscan jtag

--code für Spartan6 

--Autor René Doß

Library ieee;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

Library UNISIM;

use UNISIM.vcomponents.all;

entity jtag_tap is

   port(

        taste0 : in std_logic;

      taste1 : in std_logic;

      taste2 : in std_logic;

      taste3 : in std_logic;

        LED1 :out std_logic;

      LED2 :out std_logic;

      LED3 :out std_logic;

      LED0 :out std_logic

      );

end entity jtag_tap;

architecture syn of jtag_tap is

  signal  capture   :  std_logic := '0';  -- Test Clock

  signal  tdi       :  std_logic := '0';  -- Test Data In

  signal  tdo       :  std_logic;         -- Test Data Out

  signal  update    : std_logic;

  signal  drck      : std_logic;

  signal userreg    :  std_logic_vector(3 downto 0);

begin

   BSCAN_SPARTAN6_inst : BSCAN_SPARTAN6

   generic map (

      JTAG_CHAIN => 1  -- Value for USER command. Possible values: (1,2,3 or 4).

   )

   port map (

      CAPTURE => capture, -- 1-bit output: CAPTURE output from TAP controller.

      DRCK => drck,       -- 1-bit output: Data register output for USER functions.

      RESET => open,     -- 1-bit output: Reset output for TAP controller.

      RUNTEST => open, -- 1-bit output: Output signal that gets asserted when TAP controller is in Run Test

                          -- Idle state.

      SEL => open,         -- 1-bit output: USER active output.

      SHIFT => open,     -- 1-bit output: SHIFT output from TAP controller.

      TCK => open,         -- 1-bit output: Scan Clock output. Fabric connection to TAP Clock pin.

      TDI => TDI,         -- 1-bit output: TDI output from TAP controller.

      TMS => open,         -- 1-bit output: Test Mode Select output. Fabric connection to TAP.

      UPDATE => update,   -- 1-bit output: UPDATE output from TAP controller

      TDO => TDO          -- 1-bit input: Data input for USER function.

   );

  process(drck)

  begin  

   if update='1' then

        LED3<=userreg(3);

        LED2<=userreg(2);

      LED1<=userreg(1);

        LED0<=userreg(0);

    end if;      

   if rising_edge(drck) then

      userreg<= userreg(2 downto 0)& TDI;

      if capture='1' then

       userreg<=taste3 & taste2 &taste1 & taste0;

      end if;  

    end if;

  end process;

  tdo<=userreg(3);

end syn;