Innput data at 30MHz and Output data at 80 MHz. How to do it usgin A cyclone IV?

IMHO Dual Clock fifos are the easiest way to transferstreams to a 
different clock domain as you simply write to and read from it. Anyway, 
there are other clock domain crossing solutions -  but I would stick to 
dcfifo.

Hello friends! Yes both clocks are generated by the FPGA. 30 MHZ is the 
clock for the sensor and 80 MHz is the clock for the ETH core.

I also think that the easiest way to implement this stuff is using 
DCFIFOs

Danke schön!

30 MHz is the freq that the sensor is outputing pixels (16 bits/pixel) 
and 80 MHZ is the frequency of the ALTERA IP ETH CORE. So I need to use 
a DC FIFO to adapt both clocks.

aham I will try to do it with a buffer, Thanks!

Hello again people!!

I am testing my design with the FIFO and something strange is happening. 
The DCFIFO is able to buffering all the pixels for almost all the FRAME 
RATES that I want to set up. And here is the issue, for example when I 
set up a frame rate = 300Hz, data output is right, all the pixels are 
buffered, however when I set up a FRAME RATE = 301, I am losing the last 
4 pixels of every frame and then the data output is not right. I am 
checking the fifo full flags and there is not any overflow. Here is the 
code:

Remind: Incomming data at 30 MHZ and output data at 80MHZ

  FIFO_WR <= (VID_F_SOI or VID_F_SOL or VID_F_DAV);
  FIFO_IN <= VID_F_SOI &  VID_F_SOL &  VID_F_DAV & VID_F_DATA & 
VID_F_DARK;

  -- Clock Domain Crossing FIFO
  -- Show Ahead Mode, Output Registered
  -- Data Width 32 bits, Fifo Depth = 2**FIFO_DEPTH
  i_O_FIFO : DCFIFO
    generic map (
      CLOCKS_ARE_SYNCHRONIZED => "FALSE",
      INTENDED_DEVICE_FAMILY  => "Cyclone V",
      LPM_NUMWORDS            => 2**FIFO_DEPTH,
      LPM_SHOWAHEAD           => "ON",
      LPM_TYPE                => "dcfifo",
      LPM_WIDTH               => FIFO_WIDTH,
      LPM_WIDTHU              => FIFO_DEPTH,
      OVERFLOW_CHECKING       => "ON",
      UNDERFLOW_CHECKING      => "ON",
      USE_EAB                 => "ON",
      WRSYNC_DELAYPIPE        =>3,
      RDSYNC_DELAYPIPE        => 3,
      READ_ACLR_SYNCH         => "ON",
      WRITE_ACLR_SYNCH        => "ON"
    )
    port map (
      ACLR    => VID_I_RST,
      WRCLK   => VID_I_CLK,
      WRREQ   => FIFO_WR  ,
      DATA    => FIFO_IN  ,
      WRUSEDW => open     ,
      WRFULL  => FIFO_FUL ,
      RDCLK   => VID_O_CLK,
      RDEMPTY => FIFO_EMP ,
      RDREQ   => FIFO_RD  ,
      Q       => FIFO_OUT ,
      RDUSEDW => open
    );

  -- FIFO Full Error Detection
  process(VID_I_CLK, VID_I_RST)
  begin
    if VID_I_RST = '1' then
      FIFO_FUL_ERR <= '0';
    elsif rising_edge(VID_I_CLK) then
      if FIFO_FUL = '1' and FIFO_WR = '1' then
        FIFO_FUL_ERR <= '1';
      end if;
    end if;
  end process;

  -- Checking FIFO Flags
  process(VID_I_CLK)
  begin
    if rising_edge(VID_I_CLK) then
      assert not ( FIFO_WR = '1' and FIFO_FUL = '1' )
      report "[BINNING_4PIX] WRITE while i_O_FIFO Full !!!" severity 
failure;
    end if;
  end process;
  process(VID_O_CLK)
  begin
    if rising_edge(VID_O_CLK) then
      assert not ( FIFO_RD = '1' and FIFO_EMP = '1' )
      report "[BINNING_4PIX] READ while i_O_FIFO Empty !!!" severity 
failure;
    end if;
  end process;


Which values should I configure in the generics WRSYNC_DELAYPIPE   and 
RDSYNC_DELAYPIPE  ???

Thanks