Digitaler Lock-In-Verstärker. Wo wieviel Bit?

library IEEE;

use IEEE.std_logic_1164.ALL;

use IEEE.numeric_std.ALL;

entity lockin is 

port(  

  clock_in : in std_logic;

  enable : in std_logic;

  reset : in std_logic;

  frequency_in : in std_logic_vector(31 downto 0);

  adc_in : in std_logic_vector (13 downto 0);

  sinus_in : in std_logic_vector (13 downto 0);

  cosinus_in : in std_logic_vector (13 downto 0);

  clock_out : out std_logic;

  I_out : out std_logic_vector (17 downto 0);

  Q_out : out std_logic_vector (17 downto 0)

);

end lockin;

architecture behave of lockin is

component iir_lp

port(

      clk                             :   IN    std_logic; 

         clk_enable                      :   IN    std_logic; 

         reset                           :   IN    std_logic; 

         filter_in                       :   IN    std_logic_vector(17 DOWNTO 0); -- sfix18_En17

         filter_out                      :   OUT   std_logic_vector(17 DOWNTO 0)  -- sfix18_En12

         );

END component;

component deci

   PORT( clk                             :   IN    std_logic; 

         clk_enable                      :   IN    std_logic; 

         reset                           :   IN    std_logic; 

         filter_in                       :   IN    std_logic_vector(17 DOWNTO 0); -- sfix18_En17

         filter_out                      :   OUT   std_logic_vector(17 DOWNTO 0)  -- sfix18_En9

         );

END component;

component demodulate --get sin and coine in and multiply by adc value

generic ( sine_width : integer :=14);

port (--clock_in : in std_logic;

    fromadc_in : in Std_logic_vector (13 downto 0); 

    sine_in : in std_logic_vector (sine_width -1 downto 0); -- as 2s complement

    cosine_in : in std_logic_vector (sine_width -1 downto 0);

    output_i : out std_logic_vector (17 downto 0); --in*cos

    output_q : out std_logic_vector (17 downto 0) --in*sin

);

end component;

--signal adc_value : std_logic_vector (13 downto 0);

--signal sine_value : std_logic_vector (sine_width -1 downto 0);

--signal cosine_value : std_logic_vector (sine_width -1 downto 0);

signal multiplied_sine : std_logic_vector (17 downto 0);

signal multiplied_cosine : std_logic_vector (17 downto 0);

signal filtered1_sine : std_logic_vector (17 downto 0);

signal filtered1_cosine : std_logic_vector (17 downto 0);

signal filtered2_sine : std_logic_vector (17 downto 0);

signal filtered2_cosine : std_logic_vector (17 downto 0);

signal filtered3_sine : std_logic_vector (17 downto 0);

signal filtered3_cosine : std_logic_vector (17 downto 0);

signal decimated1_sine : std_logic_vector (17 downto 0);

signal decimated1_cosine : std_logic_vector (17 downto 0);

signal decimated2_sine : std_logic_vector (17 downto 0);

signal decimated2_cosine : std_logic_vector (17 downto 0);

signal decimated1_clock : std_logic;

signal decimated2_clock : std_logic;

signal counter1 : integer range 0 to 7;

signal counter2 : integer range 0 to 7;

--signal filtered2_sine : std_logic_vector (17 downto 0);

--signal filtered2_cosine : std_logic_vector (17 downto 0);

begin

d1 : demodulate port map(adc_in, sinus_in, cosinus_in, multiplied_cosine, multiplied_sine);

tp1cos : iir_lp port map (clock_in, enable, reset, multiplied_cosine, filtered1_cosine); -- filtered cos

tp1sin : iir_lp port map (clock_in, enable, reset, multiplied_sine, filtered1_sine); -- filtered sin

deci1 : deci port map (clock_in, enable, reset, filtered1_cosine, decimated1_cosine);

deci2 : deci port map (clock_in, enable, reset, filtered1_sine, decimated1_sine);

tp2cos : iir_lp port map (decimated1_clock, enable, reset, decimated1_cosine, filtered2_cosine); -- filtered cos

tp2sin : iir_lp port map (decimated1_clock, enable, reset, decimated1_sine, filtered2_sine); -- filtered sin

deci3 : deci port map (decimated1_clock, enable, reset, filtered2_cosine, decimated2_cosine);

deci4 : deci port map (decimated1_clock, enable, reset, filtered2_sine, decimated2_sine);

tp3cos : iir_lp port map (decimated2_clock, enable, reset, decimated2_cosine, filtered3_cosine); -- filtered cos

tp3sin : iir_lp port map (decimated2_clock, enable, reset, decimated2_sine, filtered3_sine); -- filtered sin

process (clock_in)

begin --process

if rising_edge(clock_in) then

  if (frequency_in (31 downto 29) = "000") then

    I_out <= filtered1_cosine;

    Q_out <= filtered1_sine;

    clock_out <= clock_in;

  elsif (frequency_in (28 downto 26)="000") then

    I_out <= filtered2_cosine;

    Q_out <= filtered2_sine;

    clock_out <= decimated1_clock;

  else

    I_out <= filtered3_cosine;

    Q_out <= filtered3_sine;

    clock_out <= decimated2_clock;

  end if;

end if;

end process;

process (clock_in)

begin --process

  if rising_edge(clock_in) then

    counter1 <=counter1+1;

    if (counter1=7) then

      counter2 <= counter2+1;

      decimated1_clock <= not decimated1_clock;

    end if;

    if (counter2=7) then

      decimated2_clock <= not decimated2_clock;

    end if;

  end if;

end process;

end behave;