1 | Open On-Chip Debugger 0.9.0 (2015-05-19-12:06)
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2 | Licensed under GNU GPL v2
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3 | For bug reports, read
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4 | http://openocd.org/doc/doxygen/bugs.html
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5 | Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
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6 | adapter speed: 1000 kHz
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7 | adapter_nsrst_delay: 100
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8 | none separate
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9 | srst_only separate srst_nogate srst_open_drain connect_deassert_srst
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10 | Started by GNU ARM Eclipse
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11 | Info : Unable to match requested speed 1000 kHz, using 950 kHz
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12 | Info : Unable to match requested speed 1000 kHz, using 950 kHz
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13 | Info : clock speed 950 kHz
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14 | Info : STLINK v2 JTAG v24 API v2 SWIM v11 VID 0x0483 PID 0x374B
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15 | Info : using stlink api v2
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16 | Info : Target voltage: 3.270138
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17 | Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints
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18 | Info : accepting 'gdb' connection on tcp/3333
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19 | Info : device id = 0x20036410
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20 | Info : flash size = 128kbytes
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21 | target state: halted
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22 | target halted due to debug-request, current mode: Thread
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23 | xPSR: 0x01000000 pc: 0xb9337822 msp: 0x4c05b510
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24 | semihosting is enabled
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25 | target state: halted
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26 | target halted due to debug-request, current mode: Thread
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27 | xPSR: 0x01000000 pc: 0xb9337822 msp: 0x4c05b510, semihosting
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28 | target state: halted
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29 | target halted due to breakpoint, current mode: Thread
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30 | xPSR: 0x61000000 pc: 0x2000003a msp: 0x4c05b510, semihosting
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31 | target state: halted
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32 | target halted due to debug-request, current mode: Thread
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33 | xPSR: 0x01000000 pc: 0xb9337822 msp: 0x4c05b510, semihosting
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34 | target state: halted
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35 | target halted due to debug-request, current mode: Thread
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36 | xPSR: 0x01000000 pc: 0xb9337822 msp: 0x4c05b510, semihosting
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37 | ===== arm v7m registers
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38 | (0) r0 (/32): 0x00000020
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39 | (1) r1 (/32): 0x00000000
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40 | (2) r2 (/32): 0x2000003C
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41 | (3) r3 (/32): 0x2000083C
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42 | (4) r4 (/32): 0x080005A0
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43 | (5) r5 (/32): 0x200005E4
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44 | (6) r6 (/32): 0x00000020
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45 | (7) r7 (/32): 0x00000014
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46 | (8) r8 (/32): 0xBF76FFDD
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47 | (9) r9 (/32): 0xFFBFBFFC
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48 | (10) r10 (/32): 0x304C7B31
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49 | (11) r11 (/32): 0x9C473FE3
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50 | (12) r12 (/32): 0xFF9FEFFF
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51 | (13) sp (/32): 0x4C05B510
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52 | (14) lr (/32): 0xFFFFFFFF
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53 | (15) pc (/32): 0xB9337822
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54 | (16) xPSR (/32): 0x01000000
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55 | (17) msp (/32): 0x4C05B510
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56 | (18) psp (/32): 0x34621B6C
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57 | (19) primask (/1): 0x00
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58 | (20) basepri (/8): 0x00
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59 | (21) faultmask (/1): 0x00
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60 | (22) control (/2): 0x00
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61 | ===== Cortex-M DWT registers
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62 | (23) dwt_ctrl (/32)
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63 | (24) dwt_cyccnt (/32)
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64 | (25) dwt_0_comp (/32)
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65 | (26) dwt_0_mask (/4)
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66 | (27) dwt_0_function (/32)
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67 | (28) dwt_1_comp (/32)
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68 | (29) dwt_1_mask (/4)
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69 | (30) dwt_1_function (/32)
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70 | (31) dwt_2_comp (/32)
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71 | (32) dwt_2_mask (/4)
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72 | (33) dwt_2_function (/32)
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73 | (34) dwt_3_comp (/32)
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74 | (35) dwt_3_mask (/4)
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75 | (36) dwt_3_function (/32)
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