1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.numeric_std.all;
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4 | use ieee.std_logic_misc.all;
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5 | use ieee.std_logic_arith.all;
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6 | use ieee.std_logic_unsigned.all;
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7 | USE work.reg_pack.ALL;
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8 |
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9 | library unisim;
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10 | use unisim.vcomponents.all;
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11 | library work;
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12 |
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13 | entity uart_top_ro is
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14 | port (
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15 | brd_clk : in std_logic;
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16 | rxfifo_dat : OUT STD_LOGIC_VECTOR (7 downto 0);
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17 | rx : in std_logic;
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18 | tx : out std_logic;
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19 | dat_received : OUT std_logic;
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20 | debug : OUT STD_LOGIC_VECTOR (15 downto 0)
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21 |
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22 | );
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23 | end entity;
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24 |
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25 | architecture arch_uart_top_ro of uart_top_ro is
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26 |
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27 | -- Pragma Added to supress synth warnings
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28 | --attribute DowngradeIPIdentifiedWarnings: string;
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29 | --attribute DowngradeIPIdentifiedWarnings of impl : architecture is "yes";
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30 |
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31 |
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32 | component axi_uartlite_0 is
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33 | PORT (
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34 | -- System signals
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35 | s_axi_aclk : in std_logic;
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36 | s_axi_aresetn : in std_logic;
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37 | interrupt : out std_logic;
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38 | -- AXI signals
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39 | s_axi_awaddr : in std_logic_vector(3 downto 0);
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40 | s_axi_awvalid : in std_logic;
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41 | s_axi_awready : out std_logic;
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42 | s_axi_wdata : in std_logic_vector
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43 | (31 downto 0);
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44 | s_axi_wstrb : in std_logic_vector
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45 | (3 downto 0);
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46 | s_axi_wvalid : in std_logic;
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47 | s_axi_wready : out std_logic;
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48 | s_axi_bresp : out std_logic_vector(1 downto 0);
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49 | s_axi_bvalid : out std_logic;
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50 | s_axi_bready : in std_logic;
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51 | s_axi_araddr : in std_logic_vector(3 downto 0);
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52 | s_axi_arvalid : in std_logic;
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53 | s_axi_arready : out std_logic;
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54 | s_axi_rdata : out std_logic_vector
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55 | (31 downto 0);
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56 | s_axi_rresp : out std_logic_vector(1 downto 0);
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57 | s_axi_rvalid : out std_logic;
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58 | s_axi_rready : in std_logic;
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59 |
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60 | -- UARTLite Interface Signals
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61 | rx : in std_logic;
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62 | tx : out std_logic
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63 | );
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64 | end component;
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65 |
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66 | ---------------------------------------------------------------
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67 | --Component Declaration reset_gen_ctr
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68 | component reset_gen_ctr is
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69 | port (
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70 | ck : in STD_LOGIC;
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71 | axi_nres : OUT STD_LOGIC
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72 | );
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73 | end component;
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74 |
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75 | component fsm_axi_uart_lite is
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76 | port (
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77 | ck: in std_logic;
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78 | reg_rdy: in std_logic;
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79 | rd_valid: in std_logic;
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80 | reg_sel : out std_logic;
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81 | rd_ready: out std_logic
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82 | );
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83 | end component;
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84 |
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85 | component reg_read is
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86 | port (
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87 | start : in STD_LOGIC;
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88 | reg_adr : in STD_LOGIC_VECTOR (31 downto 0);
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89 | reg_dat : OUT STD_LOGIC_VECTOR (31 downto 0);
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90 | reg_ready : OUT STD_LOGIC;
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91 | ------------------------------------------------
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92 | ax_ack : in STD_LOGIC;
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93 | ax_resetn : in STD_LOGIC;
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94 | ax_arready : in STD_LOGIC;
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95 | ax_rvalid : in STD_LOGIC;
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96 | ax_rdata : in STD_LOGIC_VECTOR (31 downto 0);
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97 | ax_arvalid : OUT STD_LOGIC;
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98 | ax_rready : OUT STD_LOGIC;
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99 | ax_ar_adr : OUT STD_LOGIC_VECTOR(31 downto 0)
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100 |
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101 | );
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102 | end component;
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103 |
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104 | signal m_axi_lite_awready : std_logic ;-- AXI4-Lite
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105 | signal m_axi_lite_awvalid : std_logic ;-- AXI4-Lite
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106 | signal m_axi_lite_awaddr : std_logic_vector (3 downto 0);-- AXI4-Lite
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107 | signal m_axi_lite_wready : std_logic ;-- AXI4-Lite
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108 | signal m_axi_lite_wvalid : std_logic ;-- AXI4-Lite
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109 | signal m_axi_lite_wdata : std_logic_vector (31 downto 0);-- AXI4-Lite
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110 | signal m_axi_lite_bready : std_logic ;-- AXI4-Lite
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111 | signal m_axi_lite_bvalid : std_logic ;-- AXI4-Lite
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112 | signal m_axi_lite_bresp : std_logic_vector(1 downto 0) ;-- AXI4-Lite
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113 | signal s_axi_lite_arready : std_logic ;-- AXI4-Lite
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114 | signal s_axi_lite_arvalid : std_logic ;-- AXI4-Lite
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115 | signal s_axi_lite_araddr : std_logic_vector (3 downto 0);-- AXI4-Lite
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116 | signal s_axi_lite_rready : std_logic ;-- AXI4-Lite
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117 | signal s_axi_lite_rvalid : std_logic ;-- AXI4-Lite
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118 | signal s_axi_lite_rdata : std_logic_vector (31 downto 0);-- AXI4-Lite
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119 | signal s_axi_lite_rresp : std_logic_vector(1 downto 0) ;-- AXI4-Lite
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120 |
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121 | signal clk: std_logic;
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122 | signal reset : std_logic;
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123 | signal reg_addr0: std_logic_vector (31 downto 0);
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124 | signal rxfifo_dat_int: std_logic_vector (7 downto 0);
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125 | signal tx_int : std_logic;
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126 | --signal dat_received_int: std_logic;
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127 | signal rd_valid0: std_logic;
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128 | signal reg_read_rdy0: std_logic;
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129 | signal rd_ready0 : std_logic;
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130 | signal reg_adr : std_logic_vector (31 downto 0);
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131 | signal reg_dat: std_logic_vector(31 downto 0);
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132 | signal ax_ar_adr: std_logic_vector(31 downto 0);
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133 | signal reg_sel1: std_logic;
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134 | signal start : std_logic;
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135 | ---
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136 | begin
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137 | clkf_buf: BUFG
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138 | port map (
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139 | I => brd_clk,
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140 | O => clk
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141 | );
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142 | --Register-Leser
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143 | uut: reg_read
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144 | port map (
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145 | start => start,
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146 | reg_adr => reg_addr0,
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147 | reg_dat => reg_dat,
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148 | reg_ready => reg_read_rdy0,
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149 | ------------------------------------------------
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150 | ax_ack => clk,
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151 | ax_resetn => reset,
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152 | ax_arready => s_axi_lite_arready,
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153 | ax_rvalid => s_axi_lite_rvalid,
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154 | ax_rdata => s_axi_lite_rdata,
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155 | ax_arvalid => s_axi_lite_arvalid,
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156 | ax_rready => s_axi_lite_rready,
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157 | ax_ar_adr => ax_ar_adr
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158 | );
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159 |
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160 | rxfifo_dat_int ( 7 downto 0 ) <= reg_dat( 7 downto 0);
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161 | s_axi_lite_araddr (3 downto 0 ) <= ax_ar_adr(3 downto 0);
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162 |
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163 | i_fsm_axi_uart_lite: fsm_axi_uart_lite
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164 | port map(
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165 | ck=> clk,
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166 | reg_rdy=> reg_read_rdy0,
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167 | rd_valid=> rd_valid0,
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168 | reg_sel=> reg_sel1,
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169 | rd_ready=> rd_ready0
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170 | );
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171 |
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172 | i_res_gen_ctr: reset_gen_ctr
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173 | port map (
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174 | ck => clk,
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175 | axi_nres => reset
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176 | );
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177 |
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178 | i_reg_data_out: reg_par
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179 | generic map (reg_width => 8)
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180 | Port map (
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181 | ck=> clk,
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182 | ld_par => rd_ready0,
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183 | data_in => rxfifo_dat_int,
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184 | data_out => rxfifo_dat
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185 | );
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186 | ual : axi_uartlite_0
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187 | PORT MAP (
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188 | interrupt => open,
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189 | s_axi_aclk => clk,
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190 | s_axi_aresetn => reset,
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191 | s_axi_awaddr => m_axi_lite_awaddr (3 downto 0),
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192 | s_axi_awvalid => m_axi_lite_awvalid,
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193 | s_axi_awready => m_axi_lite_awready,
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194 | s_axi_wdata => m_axi_lite_wdata,
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195 | s_axi_wstrb => "1111",
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196 | s_axi_wvalid => m_axi_lite_wvalid,
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197 | s_axi_wready => m_axi_lite_wready,
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198 | s_axi_bresp => m_axi_lite_bresp,
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199 | s_axi_bvalid => m_axi_lite_bvalid,
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200 | s_axi_bready => m_axi_lite_bready,
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201 | s_axi_araddr => s_axi_lite_araddr (3 downto 0),
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202 | s_axi_arvalid => s_axi_lite_arvalid,
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203 | s_axi_arready => s_axi_lite_arready,
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204 | s_axi_rdata => s_axi_lite_rdata,
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205 | s_axi_rresp => s_axi_lite_rresp,
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206 | s_axi_rvalid => s_axi_lite_rvalid,
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207 | s_axi_rready => s_axi_lite_rready,
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208 | rx => rx, -- these will go to board
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209 | tx => tx_int
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210 | );
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211 | tx <= tx_int;
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212 | ---------------------------------------------------------------
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213 | -- Mux1
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214 | reg_addr0 <= x"00000008" when reg_sel1= '0' else
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215 | x"00000000";
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216 | --Mux2
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217 | rd_valid0 <= '1' when rxfifo_dat_int(0)= '1' else
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218 | '0';
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219 | --Erst mal alles ruhigstellen:
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220 | m_axi_lite_awaddr (3 downto 0) <= "0000";
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221 | m_axi_lite_awvalid <= '0';
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222 | m_axi_lite_wdata <= (others => '0');
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223 | m_axi_lite_wvalid <= '0';
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224 | m_axi_lite_wready <= '0';
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225 | m_axi_lite_bready <= '0';
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226 |
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227 |
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228 |
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229 | --debug, an Pmod-Steckern angeschlossen:
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230 | debug(0) <= rx;
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231 | debug(1) <= '0';
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232 | debug(2) <= s_axi_lite_arvalid;
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233 | debug(3) <= s_axi_lite_arready;
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234 | debug(4) <= s_axi_lite_araddr (3);
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235 | debug(5) <= s_axi_lite_araddr (1);
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236 | debug(6) <= s_axi_lite_araddr (0);
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237 | --debug(7) <= dat_received_int;
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238 | debug(7) <= rd_ready0;
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239 | debug(15 downto 8) <= rxfifo_dat_int;
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240 |
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241 | end arch_uart_top_ro;
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