Model in LTspice

ich versuche mal diese Model in LTspice einzubinden.
leider wird ein Fehler Meldung angezeigt
" undefined subcircuit comphys2_basic_gen"

*$
* LM5146-Q1
************************************************************************ 
*****
* (C) Copyright 2018 Texas Instruments Incorporated. All rights 
reserved.
************************************************************************ 
*****
** This model is designed as an aid for customers of Texas Instruments.
** TI and its licensors and suppliers make no warranties, either 
expressed
** or implied, with respect to this model, including the warranties of
** merchantability or fitness for a particular purpose.  The model is
** provided solely on an "as is" basis.  The entire risk as to its 
quality
** and performance is with the customer
************************************************************************ 
*****
*
* This model is subject to change without notice. Texas Instruments
* Incorporated is not responsible for updating this model.
*
************************************************************************ 
*****
*
** Released by: Texas Instruments Inc.
* Part: LM5146-Q1
* Date: 11JUL2018
* Model Type:  TRANSIENT
* Simulator: PSPICE
* Simulator Version: 16.2.0.p001
* EVM Order Number: LM5146-Q1EVM-HD-20A
* EVM Users Guide:  SNVU545A-May 2017-Revised June 2017
* Datasheet: SNVSAI4 - JUNE 2017
*
* Model Version: Final 1.10
* Topologies supported: Buck
*
************************************************************************ 
*****
*
* Updates:
*
* Final 1.10
* Removed dependency of SS parameter on EN_VOUT and VREF signals.
* This dependency was disabling UVLO feature in steadystate simulations.
*
* Final 1.00
* Release to Web.
*
************************************************************************ 
*****
*
* Model Usage Notes:
*
* 1. The following features have been modeled
*      a. Current limit and SYNC feature are implemented
*      b. Maximum duty cycle, hard short response features are 
implemented
* 2. Temperature effects are not modeled.
*
************************************************************************ 
*****
.SUBCKT LM5146-Q1_TRANS AGND BST COMP EN_UVLO EP EP2 FB HO ILIM LO NC1 
NC2 PGND PGOOD
+  RT SS_TRK SW SYNCIN SYNCOUT VCC VIN
X_U4_U10         U4_N16967743 U4_N16854301 INV_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=500E-3
X_U4_U71         SW U4_SW_FB BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=5n
D_U4_D16         U4_N16854848 VDD D_D1
X_U4_S4    CLK AGND U4_N16854848 U4_N16855005 DRIVER_U4_S4
D_U4_D20         U4_N17097988 U4_ILIM_OVER_2P5 D_D2
X_U4_U61         U4_HO_LTCH U4_PRE_HO BUF_DELAY_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=0.5 DELAY=15n
X_U4_U74         POR STANDBY U4_N16855731 OR2_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=500E-3
I_U4_I2         AGND ILIM DC 100u
X_U4_U72         SW U4_ZXTH U4_N16855595 COMP_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=0.5
G_U4_ABMII8         U4_ZXTH AGND VALUE { 
LIMIT((V(U4_N16855005)*-50u),-0.5,1)
+   }
X_U4_U85         ILIM AGND U4_N16925242 U4_N16855421 COMPHYS_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
V_U4_V13         U4_N16925242 AGND 1m
V_U4_V16         U4_N16972977 AGND 2.5
X_U4_S5    U4_N16854801 AGND U4_N16855005 AGND DRIVER_U4_S5
X_U4_U42         U4_ILIM_OVER_2P5 U4_N16976073 U4_ILIM_SET N16979513
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U4_U91         PWML U4_N17063432 INV_DELAY_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=0.5 DELAY=25n
X_U4_U68         LO U4_LO_FB_B INV_BASIC_GEN PARAMS: VDD=1 VSS=0 
VTHRESH=500E-3
X_U4_U73         U4_EN_ILIMIT U4_N16855595 U4_N16855600 AND2_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
G_U4_G2         AGND ILIM U4_N16855429 AGND 20u
X_U4_U38         U4_LO_LTCH U4_EN_ILIMIT U4_ILIM_COMP ILIMITX 
AND3_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
X_U4_U18         STANDBY U4_N16854380 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
I_U4_I1         VDD U4_N16854848 DC 250u
X_U4_U87         U4_BST_SW U4_N16958239 U4_N16957918 U4_BOOT_UVLO
+  COMPHYS2_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 T=10
X_U4_U64         U4_PRE_HO U4_N16855352 INV_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=500E-3
X_U4_U62         U4_N17063432 U4_N17063430 U4_N17067290 OR2_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U4_U88         ILIM U4_N16972977 U4_ILIM_OVER_2P5 COMP_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U4_U57         U4_ILIM_OVER_2P5 U4_N17097988 BUF_DELAY_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5 DELAY=20n
X_U4_U39         U4_HO_LTCH U4_N16854747 U4_N16854794 U4_N16854801
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U4_U86         U4_N16950199 U4_N16878613 one_shot PARAMS:  T=22
X_U4_U65         U4_LO_LTCH U4_PRE_LO BUF_DELAY_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=0.5 DELAY=15n
X_U4_U67         STANDBY U4_N16855600 U4_N16855640 OR2_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=500E-3
X_U4_U69         U4_N16855005 U4_N16855433 BUF_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=0.5
X_U4_S6    U4_PRE_HO AGND BST HO DRIVER_U4_S6
X_U4_U43         U4_N17097988 U4_N16855731 U4_N16855429 N17102863
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=5 VSS=0 VTHRESH=0.5
X_U4_U81         U4_ENABLELO U4_N17067290 U4_LO_LTCH AND2_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
C_U4_C4         U4_N16855005 AGND  4n
X_U4_U83         DEMBFLTR U4_N16855496 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
V_U4_V14         U4_N16957918 AGND 0.13
X_U4_S12    U4_N16855352 AGND HO SW DRIVER_U4_S12
D_U4_D18         VCC BST D_D2
X_U4_U89         EN_VOUT U4_N16976073 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U4_U92         U4_N16855421 U4_ILIM_COMP INV_DELAY_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=0.5 DELAY=20n
X_U4_U78         LO U4_EN_ILIMIT BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=0.5 DELAY=20n
V_U4_V15         U4_N16958239 AGND 3.75
X_U4_U30         U4_N16854461 U4_N16855433 U4_ENABLELO OR2_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U4_U90         U4_N17063432 U4_N17063430 one_shot PARAMS:  T=90
R_U4_R8         U4_ZXTH U4_N16855517  1k
D_U4_D19         U4_EN_ILIMIT LO D_D2
X_U4_U9         U4_N16855640 U4_HO_LTCH U4_ZXL U4_N16854461
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U4_U80         U4_N16854380 U4_SR_OUT U4_N16950199 AND2_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
V_U4_V12         U4_N16855517 AGND -5m
X_U4_U66         U4_PRE_LO U4_N16855224 INV_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=500E-3
X_U4_S13    U4_PRE_LO AGND U4_N16855274 LO DRIVER_U4_S13
C_U4_C5         U4_N16854794 AGND  4n
X_U4_U82         PWML U4_BOOT_UVLO U4_N16967743 AND2_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=500E-3
X_U4_U33         STANDBY U4_N16855496 U4_N16854747 OR2_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=500E-3
X_U4_U60         U4_SR_OUT U4_N16878613 U4_HO_LTCH OR2_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=500E-3
E_U4_E1         U4_BST_SW AGND BST SW 1
X_U4_U8         U4_LO_FB_B U4_N16854301 U4_SR_OUT N16855463
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U4_S14    U4_N16855224 AGND LO AGND DRIVER_U4_S14
E_U4_E3         U4_N16855274 AGND VCC AGND 1
D_U1_D7         U1_N16787350 COMP_CLAMP_CHG D_D2
E_U1_E5         U1_N16811554 AGND VREF U1_FB_EA 10000
V_U1_V2         U1_N16737804 U1_FB_EA 0.135
E_U1_E4         U1_N16787350 U1_RAMP_OFF VIN_INT AGND 6.6666m
V_U1_V5         U1_RAMP_OFF AGND 300m
X_U1_U3         EN_VOUT U1_N16689495 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
D_U1_D8         COMP_CLAMP_CHG U1_N16787666 D_D2
R_U1_R4         SS_TRK VREF  10k
X_U1_S3    PWML AGND IRAMP U1_RAMP_OFF ERRORAMP_U1_S3
D_U1_D9         COMP_CLAMP_DISCHG U1_N16836988 D_D2
V_U1_V4         U1_N16787666 U1_N16787695 0.2
D_U1_D10         COMP U1_N16815648 D_D2
I_U1_I1         U1_N01140 SS_TRK DC 10u
E_U1_E3         U1_N16787695 COMP VIN_INT AGND 11.111111m
D_U1_D4         SS_TRK U1_N16737804 D_D2
X_U1_S4    VALLEY_PWM AGND COMP_CLAMP_DISCHG AGND ERRORAMP_U1_S4
C_U1_C3         IRAMP U1_RAMP_OFF  5p
X_U1_U4         POR HICCUPTIMEOUT U1_N16689495 STANDBY OR3_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
V_U1_V1         U1_N01140 AGND 0.8
R_U1_R5         U1_N16811554 COMP  276
C_U1_C4         COMP_CLAMP_CHG AGND  5p
V_U1_V8         U1_N16815648 AGND 5
X_U1_F1    U1_N16836988 AGND COMP_CLAMP_CHG AGND ERRORAMP_U1_F1
C_U1_C2         COMP AGND  1u IC=0
D_U1_D6         U1_N168082641 COMP D_D2
X_U1_S2    STANDBY AGND SS_TRK AGND ERRORAMP_U1_S2
R_U1_R3         FB U1_FB_EA  1k
V_U1_V7         U1_N168082641 AGND 100m
X_U1_U5         IRAMP COMP_CLAMP_CHG COMP_CLAMP COMP_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=0.5
D_U1_D5         U1_N167374381 U1_FB_EA D_D2
V_U1_V3         U1_N167374381 AGND 0.06
D_U1_D3         VREF U1_N01140 D_D2
X_U5_U86         U5_N16786127 U5_RESET U5_N16785473 U5_N16785488
+  SRLATCHSHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
R_U5_R9         U5_N16785903 AGND  20k
X_U5_S15    U5_N16785583 AGND U5_N16785384 AGND Oscillator_SYNC_U5_S15
X_U5_S16    U5_N16785745 AGND U5_IOSC_BOT AGND Oscillator_SYNC_U5_S16
E_U5_E4         U5_N16785923 AGND U5_N16785903 AGND 1
X_U5_U98         U5_N16785923 U5_N16786177 INV_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=500E-3
X_U5_U81         U5_N16785488 POR U5_N16785438 OR2_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=500E-3
X_U5_S17    U5_N16785438 AGND IOSC AGND Oscillator_SYNC_U5_S17
X_U5_U89         U5_N16785983 N16785815 U5_N16785923 VDD DEMBFLTR 
U5_GND_INV
+  DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U5_C8         U5_IOSC_BOT AGND  5p
X_U5_U82         U5_N16785863 U5_SYNCSET one_shot PARAMS:  T=80
X_U5_U87         U5_N16786177 POR DEMBFLTR NOR2_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=500E-3
X_U5_U90         U5_N16786039 N16785842 U5_N16785983 U5_N16785923 
DEMBFLTR
+  U5_GND_INV DFFSBRB_RHPBASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
V_U5_V1         U5_N16792634 AGND 2
X_U5_U91         U5_N16785473 SYNCOUT INV_BASIC_GEN PARAMS: VDD=3 VSS=0
+  VTHRESH=500E-3
X_U5_U88         U5_N16785473 POR U5_N16785745 OR2_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=500E-3
X_U5_U92         U5_N16785923 U5_N16786039 U5_N16785863 AND2_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U5_U93         U5_SET U5_N16785792 N16785380 U5_N16785583
+  SRLATCHSHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U5_U83         U5_IOSC_BOT VINBY30 U5_SET COMP_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=0.5
X_U5_U84         IOSC VINBY30 U5_RESET COMP_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=0.5
X_U5_U94         AGND U5_GND_INV INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
E_U5_E3         U5_N16785792 AGND U5_SYNCSET AGND 1
G_U5_ABMII9         AGND U5_N16785384 VALUE { LIMIT
+ {(V(I_VIN_25_GND)*41.666m),0,7.5}    }
X_U5_U99         SYNCIN U5_N16792634 U5_N16785903 COMP_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=0.5
C_U5_C7         IOSC AGND  5p
X_U5_U85         U5_N16785473 CLK one_shot PARAMS:  T=80
G_U5_ABMII10         AGND U5_IOSC_BOT VALUE { LIMIT
+ {(V(I_VIN_25_GND)*41.666m),0,7.5}    }
X_U5_U95         U5_SYNCSET U5_N16786111 U5_N16786127 OR2_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U5_U80         U5_SET EN_VOUT U5_N16786111 AND2_BASIC_GEN PARAMS: 
VDD=1 VSS=0
+  VTHRESH=500E-3
D_U5_D20         U5_N16785384 U5_IOSC_BOT D_D1
V_U3_V4         U3_N16800602 AGND 0.852
E_U3_E1         U3_N16682856 AGND VIN_INT AGND 1
R_U3_R2         U3_VINBY25 VINBY30  100
X_U3_U31         POR U3_N16802890 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U3_U14         U3_N16800195 U3_N16800229 BUF_DELAY_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=0.5 DELAY=25u
V_U3_V1         U3_TEST AGND 1.2
V_U3_V7         U3_N16800294 AGND 24m
X_U3_U26         U3_N16763833 U3_N167719751 INV_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=500E-3
X_U3_U22         U3_OV U3_N16800179 U3_UV U3_N16800211 OR3_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
E_U3_ABM1         U3_N16682914 0 VALUE { IF(V(U3_VINBY25)<7.5, 
(V(U3_VINBY25)),
+  7.5)    }
D_U3_D3         U3_N16800524 U3_N16800209 D_D1
R_U3_R5         U3_N167719751 U3_N16771999  5
V_U3_V5         U3_N16800174 AGND 0.748
C_U3_C4         U3_N16771999 AGND  1n
X_U3_U20         POR U3_N16800185 U3_N16800179 OR2_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=500E-3
V_U3_V6         U3_N16800223 AGND 24m
G_U3_ABMII1         AGND COMP_CLAMP_CHG VALUE {
+  LIMIT((V(I_VIN_25_GND)*8.3m),7.5,0)    }
X_U3_U7         U3_N16691404 EN_UVLO_INT POR COMP_BASIC_GEN PARAMS: 
VDD=1 VSS=0
+  VTHRESH=0.5
G_U3_ABMII2         AGND COMP_CLAMP_DISCHG VALUE {
+  LIMIT((V(I_VIN_25_GND)*16.7m),0,7.5)    }
D_U3_D2         U3_N16800229 U3_N16800195 D_D1
X_U3_U17         U3_N16800207 U3_N16800558 BUF_DELAY_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=0.5 DELAY=25u
D_U3_D5         U3_N16800558 U3_N16800207 D_D1
X_U3_U16         U3_N16800201 U3_N16800541 BUF_DELAY_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=0.5 DELAY=25u
X_U3_U25         U3_N16772539 U3_N16771999 EN_VOUT N16769878
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U3_U27         FB U3_N16800174 U3_N16800294 U3_N16800201 
COMPHYS_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
V_U3_V2         U3_N16691404 AGND 0.4
R_U3_R3         VINBY30 AGND  500
X_U3_U30         FB U3_N16800602 U3_N16800223 U3_N16800195 
COMPHYS_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U3_U28         U3_N16800541 U3_N16800558 N16800586 U3_UV 
SRLATCHRHP_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
R_U3_R1         U3_N16682856 U3_VINBY25  14.4k
X_U3_U12         U3_N16800195 U3_N16800209 INV_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=500E-3
E_U3_ABM4         VCC 0 VALUE { IF(V(U3_N16802890)>0.5, 7.5,0)    }
D_U3_D4         U3_N16800541 U3_N16800201 D_D1
C_U3_C3         U3_N16772539 AGND  1n IC=1
X_U3_H1    U3_N16682914 RT I_VIN_25_GND AGND HOUSE_KEEPING_U3_H1
X_U3_U3         EN_UVLO_INT U3_TEST U3_N16763833 COMP_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=0.5
X_U3_U13         U3_N16800201 U3_N16800207 INV_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=500E-3
X_U3_U15         U3_N16800209 U3_N16800524 BUF_DELAY_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=0.5 DELAY=25u
X_U3_U21         EN_VOUT U3_N16800185 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
G_U3_ABMII3         AGND IRAMP VALUE { 
LIMIT((V(I_VIN_25_GND)*83m),7.5,0)    }
X_U3_U29         U3_N16800229 U3_N16800524 U3_OV N16800591 
SRLATCHRHP_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_U3_ABM3         VDD 0 VALUE { IF(V(EN_VOUT)>0.5, 5,0)    }
R_U3_R4         U3_N16763833 U3_N16772539  5
G_U3_ABMII4         AGND IOSC VALUE { LIMIT((V(I_VIN_25_GND)*83m),7.5,0) 
}
X_U3_S4    U3_N16800211 AGND PGOOD AGND HOUSE_KEEPING_U3_S4
E_E1         VIN_INT AGND VIN AGND 1
G_U6_G1         AGND U6_N16745668 U6_N16745614 AGND 0.02
X_U6_U26         U6_N16784881 U6_N16785284 INV_DELAY_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=0.5 DELAY=10n
E_U6_ABM1         U6_N16745796 0 VALUE {
+  IF(V(U6_N16745696)>V(U6_N16745778),1,0)    }
D_U6_D6         U6_N16746128 U6_N16746156 D_D2
D_U6_D5         U6_N16745668 U6_N16745696 D_D2
X_U6_U22         U6_N16784881 U6_N16785284 U6_N16784738 AND2_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U6_U25         U6_N16765692 CLK U6_N16783339 U6_N16784881 
AND3_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U6_C2         U6_N16746156 AGND  1n
X_U6_U27         CLK U6_N16787778 U6_8192CYCLE U6_N16746446 
AND3_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=500E-3
C_U6_C1         U6_N16745696 AGND  1n
X_U6_U16         U6_N16756861 POR U6_8192CYCLE_RESET OR2_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U6_U7         U6_N16746156 U6_N16746244 U6_8192CYCLE COMP_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=0.5
X_U6_U21         VALLEY_PWM U6_N16783339 INV_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=500E-3
V_U6_V2         U6_N16746244 AGND 819.3
X_U6_U4         U6_N16745796 U6_N16746410 HICCUPTIMEOUT N16746044
+  SRLATCHRHP_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5
V_U6_V1         U6_N16745778 AGND 128
X_U6_U8         U6_8192CYCLE U6_N16756861 BUF_DELAY_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=0.5 DELAY=50n
X_U6_U5         CLK HICCUPTIMEOUT U6_8192_START AND2_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=500E-3
X_U6_U15         POR U6_8192CYCLE_RESET U6_N16746410 OR2_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U6_U18         HICCUPTIMEOUT U6_N16765692 INV_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=500E-3
X_U6_S2    U6_8192CYCLE_RESET AGND U6_N16746156 AGND HICCUP_U6_S2
X_U6_U6         U6_8192_START U6_N16746074 one_shot PARAMS:  T=50
X_U6_S1    U6_N16745882 AGND U6_N16745696 AGND HICCUP_U6_S1
X_U6_U17         STANDBY COMP_CLAMP U6_N16787778 OR2_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=500E-3
X_U6_U1         U6_N16784738 U6_N16745614 one_shot PARAMS:  T=50
X_U6_U28         U6_N16746446 STANDBY NPWM U6_N16745882 AND3_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
G_U6_G2         AGND U6_N16746128 U6_N16746074 AGND 0.02
X_U2_U4         CLK U2_N16689730 INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U2_U5         CLK U2_ILIMITX_N U2_N16690230 VALLEY_PWM 
SRLATCHRHP_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
C_U2_C3         U2_N16690230 AGND  5p
X_U2_U2         CLK U2_N16695634 U2_N16688726 N16688771 
SRLATCHRHP_BASIC_GEN
+  PARAMS: VDD=1 VSS=0 VTHRESH=0.5
X_U2_U9         NPWM STANDBY COMP_CLAMP U2_N16695634 OR3_BASIC_GEN 
PARAMS:
+  VDD=1 VSS=0 VTHRESH=500E-3
X_U2_U3         U2_N16689730 U2_N16688726 U2_PWM AND2_BASIC_GEN PARAMS: 
VDD=1
+  VSS=0 VTHRESH=500E-3
X_U2_U7         ILIMITX U2_ILIMITX_N INV_BASIC_GEN PARAMS: VDD=1 VSS=0
+  VTHRESH=500E-3
X_U2_U6         VALLEY_PWM U2_PWM PWML AND2_BASIC_GEN PARAMS: VDD=1 
VSS=0
+  VTHRESH=500E-3
X_U2_U10         IRAMP COMP NPWM COMP_BASIC_GEN PARAMS: VDD=1 VSS=0 
VTHRESH=0.5
E_E2         EN_UVLO_INT AGND EN_UVLO AGND 1
.ENDS LM5146-Q1_TRANS
*$
.subckt DRIVER_U4_S4 1 2 3 4
S_U4_S4         3 4 1 2 _U4_S4
RS_U4_S4         1 2 1G
.MODEL         _U4_S4 VSWITCH Roff=1e9 Ron=1m Voff=0.2 Von=0.8
.ends DRIVER_U4_S4
*$
.subckt DRIVER_U4_S5 1 2 3 4
S_U4_S5         3 4 1 2 _U4_S5
RS_U4_S5         1 2 1G
.MODEL         _U4_S5 VSWITCH Roff=1e9 Ron=1m Voff=0.2 Von=0.8
.ends DRIVER_U4_S5
*$
.subckt DRIVER_U4_S6 1 2 3 4
S_U4_S6         3 4 1 2 _U4_S6
RS_U4_S6         1 2 1G
.MODEL         _U4_S6 VSWITCH Roff=1e7 Ron=1.42 Voff=0.2 Von=0.8
.ends DRIVER_U4_S6
*$
.subckt DRIVER_U4_S12 1 2 3 4
S_U4_S12         3 4 1 2 _U4_S12
RS_U4_S12         1 2 1G
.MODEL         _U4_S12 VSWITCH Roff=1e7 Ron=0.85 Voff=0.2 Von=0.8
.ends DRIVER_U4_S12
*$
.subckt DRIVER_U4_S13 1 2 3 4
S_U4_S13         3 4 1 2 _U4_S13
RS_U4_S13         1 2 1G
.MODEL         _U4_S13 VSWITCH Roff=1e7 Ron=1.42 Voff=0.2 Von=0.8
.ends DRIVER_U4_S13
*$
.subckt DRIVER_U4_S14 1 2 3 4
S_U4_S14         3 4 1 2 _U4_S14
RS_U4_S14         1 2 1G
.MODEL         _U4_S14 VSWITCH Roff=1e7 Ron=0.85 Voff=0.2 Von=0.8
.ends DRIVER_U4_S14
*$
.subckt ERRORAMP_U1_S3 1 2 3 4
S_U1_S3         3 4 1 2 _U1_S3
RS_U1_S3         1 2 1G
.MODEL         _U1_S3 VSWITCH Roff=1e9 Ron=10 Voff=0.8 Von=0.2
.ends ERRORAMP_U1_S3
*$
.subckt ERRORAMP_U1_S4 1 2 3 4
S_U1_S4         3 4 1 2 _U1_S4
RS_U1_S4         1 2 1G
.MODEL         _U1_S4 VSWITCH Roff=100e6 Ron=1 Voff=0.2 Von=0.8
.ends ERRORAMP_U1_S4
*$
.subckt ERRORAMP_U1_F1 1 2 3 4
F_U1_F1         3 4 VF_U1_F1 1
VF_U1_F1         1 2 0V
.ends ERRORAMP_U1_F1
*$
.subckt ERRORAMP_U1_S2 1 2 3 4
S_U1_S2         3 4 1 2 _U1_S2
RS_U1_S2         1 2 1G
.MODEL         _U1_S2 VSWITCH Roff=1e9 Ron=12 Voff=0.2 Von=0.8
.ends ERRORAMP_U1_S2
*$
.subckt Oscillator_SYNC_U5_S15 1 2 3 4
S_U5_S15         3 4 1 2 _U5_S15
RS_U5_S15         1 2 1G
.MODEL         _U5_S15 VSWITCH Roff=1e9 Ron=1 Voff=0.2 Von=0.8
.ends Oscillator_SYNC_U5_S15
*$
.subckt Oscillator_SYNC_U5_S16 1 2 3 4
S_U5_S16         3 4 1 2 _U5_S16
RS_U5_S16         1 2 1G
.MODEL         _U5_S16 VSWITCH Roff=1e9 Ron=10 Voff=0.2 Von=0.8
.ends Oscillator_SYNC_U5_S16
*$
.subckt Oscillator_SYNC_U5_S17 1 2 3 4
S_U5_S17         3 4 1 2 _U5_S17
RS_U5_S17         1 2 1G
.MODEL         _U5_S17 VSWITCH Roff=1e9 Ron=10 Voff=0.2 Von=0.8
.ends Oscillator_SYNC_U5_S17
*$
.subckt HOUSE_KEEPING_U3_H1 1 2 3 4
H_U3_H1         3 4 VH_U3_H1 1
VH_U3_H1         1 2 0V
.ends HOUSE_KEEPING_U3_H1
*$
.subckt HOUSE_KEEPING_U3_S4 1 2 3 4
S_U3_S4         3 4 1 2 _U3_S4
RS_U3_S4         1 2 1G
.MODEL         _U3_S4 VSWITCH Roff=1e9 Ron=50 Voff=0.2 Von=0.8
.ends HOUSE_KEEPING_U3_S4
*$
.subckt HICCUP_U6_S2 1 2 3 4
S_U6_S2         3 4 1 2 _U6_S2
RS_U6_S2         1 2 1G
.MODEL         _U6_S2 VSWITCH Roff=1e9 Ron=10m Voff=0.0V Von=1.0V
.ends HICCUP_U6_S2
*$
.subckt HICCUP_U6_S1 1 2 3 4
S_U6_S1         3 4 1 2 _U6_S1
RS_U6_S1         1 2 1G
.MODEL         _U6_S1 VSWITCH Roff=1e9 Ron=10m Voff=0.0V Von=1.0V
.ends HICCUP_U6_S1
*$
.SUBCKT AND2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND2_BASIC_GEN
*$
.SUBCKT AND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH} &
+ V(D) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS AND4_BASIC_GEN
*$
.SUBCKT NAND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NAND3_BASIC_GEN
*$
.SUBCKT NAND4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  &
+ V(B) > {VTHRESH} &
+ V(C) > {VTHRESH} &
+ V(D) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NAND4_BASIC_GEN
*$
.SUBCKT OR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR2_BASIC_GEN
*$
.SUBCKT OR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR3_BASIC_GEN
*$
.SUBCKT OR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH} |
+ V(D) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS OR4_BASIC_GEN
*$
.SUBCKT NOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |
+ V(B) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR2_BASIC_GEN
*$
.SUBCKT NOR3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR3_BASIC_GEN
*$
.SUBCKT NOR4_BASIC_GEN A B C D Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH} |
+ V(D) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR4_BASIC_GEN
*$
.SUBCKT NOR5_BASIC_GEN A B C D E Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH} |
+ V(D) > {VTHRESH} |
+ V(E) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR5_BASIC_GEN
*$
.SUBCKT NOR6_BASIC_GEN A B C D E F Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE YINT 0 VALUE {{IF(V(A) > {VTHRESH}  |
+ V(B) > {VTHRESH} |
+ V(C) > {VTHRESH} |
+ V(D) > {VTHRESH} |
+ V(E) > {VTHRESH} |
+ V(F) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS NOR6_BASIC_GEN
*$
.SUBCKT INV_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH} ,
+ {VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1p
.ENDS INV_BASIC_GEN
*$
.SUBCKT XOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE  YINT 0 VALUE {{IF(V(A) > {VTHRESH}  ^
+ V(B) > {VTHRESH},{VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS XOR2_BASIC_GEN
*$
.SUBCKT XNOR2_BASIC_GEN A B Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE  YINT 0 VALUE {{IF(V(A) > {VTHRESH}  ^
+ V(B) > {VTHRESH},{VSS},{VDD})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS XNOR2_BASIC_GEN
*$
.SUBCKT INV_DELAY_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 
10n
E_ABMGATE1    YINT1 0 VALUE {{IF(V(A) > {VTHRESH} ,
+ {VDD},{VSS})}}
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.3}
E_ABMGATE2    YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} ,
+ {VSS},{VDD})}}
RINT2 YINT3 Y 1
CINT2 Y 0 1n
.ENDS INV_DELAY_BASIC_GEN
*$
.SUBCKT BUF_DELAY_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 
10n
E_ABMGATE1    YINT1 0 VALUE {{IF(V(A) > {VTHRESH} ,
+ {VDD},{VSS})}}
RINT YINT1 YINT2 1
CINT YINT2 0 {DELAY*1.3}
E_ABMGATE2    YINT3 0 VALUE {{IF(V(YINT2) > {VTHRESH} ,
+ {VDD},{VSS})}}
RINT2 YINT3 Y 1
CINT2 Y 0 1n
.ENDS BUF_DELAY_BASIC_GEN
*$
.SUBCKT BUF_BASIC_GEN A  Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    YINT 0 VALUE {{IF(V(A) > {VTHRESH} ,
+ {VDD},{VSS})}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS BUF_BASIC_GEN
*$
.SUBCKT SRLATCHSHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5
GQ 0 Qint VALUE = {IF(V(S) > {VTHRESH},5,IF(V(R)>{VTHRESH},-5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS}
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1
Cdummy1 Q 0 1n
Cdummy2 QB 0 1n
.IC V(Qint) {VSS}
.ENDS SRLATCHSHP_BASIC_GEN
*$
.SUBCKT SRLATCHRHP_BASIC_GEN S R Q QB PARAMS: VDD=1 VSS=0 VTHRESH=0.5
GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S)>{VTHRESH},5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D1
V2 MYVSS 0 {VSS}
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1
Cdummy1 Q 0 1n
Cdummy2 QB 0 1n
.IC V(Qint) {VSS}
.ENDS SRLATCHRHP_BASIC_GEN
*$
.SUBCKT SBRBLATCHRHP_BASIC_GEN SB RB Q QB PARAMS: VDD=1 VSS=0 
VTHRESH=0.5
GQ 0 Qint VALUE = {IF(V(RB) < {VTHRESH},-5,IF(V(SB) < {VTHRESH},5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D2
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D2
V2 MYVSS 0 {VSS}
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1
.IC V(Qint) {VSS}
.ENDS SBRBLATCHRHP_BASIC_GEN
*$
.SUBCKT SBRBLATCHSHP_BASIC_GEN SB RB Q QB PARAMS: VDD=1 VSS=0 
VTHRESH=0.5
GQ 0 Qint VALUE = {IF(V(SB) < {VTHRESH},5,IF(V(RB) < {VTHRESH},-5, 0))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D2
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D2
V2 MYVSS 0 {VSS}
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH={VTHRESH}
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr QB 1
.IC V(Qint) {VSS}
.ENDS SBRBLATCHSHP_BASIC_GEN
*$
.SUBCKT DFFSBRB_SHPBASIC_GEN Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 
VTHRESH=0.5
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} 
VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} 
VTHRESH={VTHRESH}
GQ 0 Qint VALUE = {IF(V(SB) < {VTHRESH},5,IF(V(RB)<{VTHRESH},-5, 
IF(V(CLKint)> {VTHRESH},
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D2
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D2
V2 MYVSS 0 {VSS}
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} 
VTHRESH={VTHRESH} DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1
Cdummy1 Q 0 1nF
Cdummy2 QB 0 1nF
.IC V(Qint) {VSS}
.ENDS DFFSBRB_SHPBASIC_GEN
*$
.SUBCKT DFFSR_SHPBASIC_GEN Q QB CLK D R S PARAMS: VDD=1 VSS=0 
VTHRESH=0.5
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} 
VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} 
VTHRESH={VTHRESH}
GQ 0 Qint VALUE = {IF(V(S) > {VTHRESH},5,IF(V(R) > {VTHRESH},-5, 
IF(V(CLKint)> {VTHRESH},
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D2
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D2
V2 MYVSS 0 {VSS}
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD=1 VSS=0 VTHRESH=0.5 DELAY = 
20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1
Cdummy1 Q 0 1nF
Cdummy2 QB 0 1nF
.IC V(Qint) {VSS}
.ENDS DFFSR_SHPBASIC_GEN
*$
.SUBCKT DFFSBRB_RHPBASIC_GEN Q QB CLK D RB SB PARAMS: VDD=1 VSS=0 
VTHRESH=0.5
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} 
VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} 
VTHRESH={VTHRESH}
GQ 0 Qint VALUE = {IF(V(RB) < {VTHRESH},-5,IF(V(SB)< {VTHRESH},5, 
IF(V(CLKint)> {VTHRESH},
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D1
V1 MY5 0 5
D_D11 0 Qint D_D1
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} 
VTHRESH={VTHRESH} DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1
Cdummy1 Q 0 1nF
Cdummy2 QB 0 1nF
.IC V(Qint) {VSS}
.ENDS DFFSBRB_RHPBASIC_GEN
*$
.SUBCKT DFFSR_RHPBASIC_GEN Q QB CLK D R S PARAMS: VDD=1 VSS=0 
VTHRESH=0.5
X1 CLK CLKdel INV_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} 
VTHRESH={VTHRESH} DELAY = 15n
X2 CLK CLKdel CLKint AND2_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} 
VTHRESH={VTHRESH}
GQ 0 Qint VALUE = {IF(V(R) > {VTHRESH},-5,IF(V(S) > {VTHRESH},5, 
IF(V(CLKint)> {VTHRESH},
+ IF(V(D)> {VTHRESH},5,-5),0)))}
CQint Qint 0 1n
RQint Qint 0 1000MEG
D_D10 Qint MY5 D_D2
V1 MY5 0 {VDD}
D_D11 MYVSS Qint D_D2
V2 MYVSS 0 {VSS}
EQ Qqq 0 Qint 0 1
X3 Qqq Qqqd1 BUF_DELAY_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} 
VTHRESH={VTHRESH} DELAY = 20n
RQq Qqqd1 Q 1
EQb Qbr 0 VALUE = {IF( V(Q) > {VTHRESH}, {VSS},{VDD})}
RQb Qbr Qb 1
Cdummy1 Q 0 1nF
Cdummy2 QB 0 1nF
.IC V(Qint) {VSS}
.ENDS DFFSR_RHPBASIC_GEN
*$
.model NMOS02 NMOS
+ VTO     = 2.5
+ KP     = 0.8
+ LAMBDA  = 0.001
*$
.model NMOS01 NMOS
+ VTO     = 2
+ KP      = 0.5555
+ LAMBDA  = 0.001
*$
.model PMOS01 PMOS
+ VTO     = -2
+ KP      = .889
+ LAMBDA  = 0.001
*$
.SUBCKT FALLING_DELAY IN OUT PARAMS: DELAY=100n VDD=1 VSS=0 VTHRESH=0.5
X_U1         INT OUT BUF_BASIC_GEN PARAMS: VDD={VDD} VSS={VSS} VTHRESH=
+ {VTHRESH}
R_R1         IN INT  {DELAY/(0.693 * 1E-9)}
C_C1         0 INT  1n
D_D11         IN INT DD
.MODEL DD D( IS=1F N=0.01 TT = 10p )
.ENDS FALLING_DELAY
*$
.SUBCKT Z_IDEAL A C PARAMS: RS = 1 VTH = 6.4
G1 A C VALUE { MIN(0, ( V(A) - V(C) + { VTH } ) / { RS } ) }
R1 A C 1G
.ENDS Z_IDEAL
*$
.SUBCKT COMPHYS_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 
VTHRESH=0.5
EIN INP1 INM1 INP INM 1
EHYS INP1 INP2 VALUE { IF( V(1) > {VTHRESH},-V(HYS),0) }
EOUT OUT 0 VALUE { IF( V(INP2)>V(INM1), {VDD} ,{VSS}) }
R1 OUT 1 1
C1 1 0 5n
RINP1 INP1 0 1K
.ENDS COMPHYS_BASIC_GEN
*$
.SUBCKT AND3_BASIC_GEN A B C Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE    Y 0 VALUE {{IF(V(A) > {VTHRESH}  &  + V(B) > {VTHRESH} & + 
V(C) > {VTHRESH},{VDD},{VSS})}}
.ENDS AND3_BASIC_GEN
*$
.SUBCKT COMP_BASIC_GEN INP INM Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABM Yint 0 VALUE {IF (V(INP) > + V(INM), {VDD},{VSS})}
R1 Yint Y 1
C1 Y 0 1n
.ENDS COMP_BASIC_GEN
*$
.SUBCKT MUX2_BASIC_GEN A B S Y PARAMS: VDD=1 VSS=0 VTHRESH=0.5
E_ABMGATE  YINT 0 VALUE {{IF(V(S) > {VTHRESH},  + V(B),V(A))}}
RINT YINT Y 1
CINT Y 0 1n
.ENDS MUX2_BASIC_GEN
*$
.subckt Var_Resistor_HIGH IN VCC GND O+ O-
E_RVAL RVAL GND 
VALUE={(0.03787*V(VCC)*V(VCC)-1.02313*V(VCC)+13.2713)*(1-V(IN)) + 
V(IN)*1e6}
R_ERVAL RVAL GND 1G
G_R O+ O- VALUE={V(O+,O-)/(V(RVAL))}
ROUT O+ O- 1G
.ENDS
*$
.subckt Var_Resistor_LOW IN VCC GND O+ O-
E_RVAL RVAL GND 
VALUE={(0.0303*V(VCC)*V(VCC)-0.728*V(VCC)+11.0737)*V(IN)+ (1-V(IN))*1e6}
R_ERVAL RVAL GND 1G
G_R O+ O- VALUE={V(O+,O-)/(V(RVAL))}
ROUT O+ O- 1G
.ENDS
*$
.subckt Var_Resistor_PROP VCC GND O+ O-
E_RVAL RVAL GND VALUE={0.3206*V(VCC)*V(VCC)-7.696*V(VCC)+70.963}
R_ERVAL RVAL GND 1G
G_R O+ O- VALUE={V(O+,O-)/(V(RVAL))}
ROUT O+ O- 1G
.ENDS
*$
.SUBCKT LM3414Q1 D G S Bulk
M1x D G S Bulk LM3414Q1
.MODEL LM3414Q1 NMOS Level=1 CBD=26.5p CBS=31.8p CGBO=142n
+ CGDO=640n CGSO=768n GAMMA=1.59 IS=250f KP=0.968
+ LAMBDA=0.116 MJ=0.460 PB=0.800 PHI=.75 RD=0.108 RS=0.108
+ VTO=2
.ENDS
*$
.SUBCKT NMOS_1 D G S B PARAMS: L=1U W=1U
M1   D G S B  DMOS L=1U W=1U
.MODEL DMOS NMOS(LEVEL=3 VMAX=625k THETA=900m
+ ETA=2.00m VTO=2 KP=107 lambda=0.01
.ENDS
*$
.SUBCKT D_IDEAL A C PARAMS: RS = 1 VTH = 0.7
G1 A C VALUE { MAX(0, ( V(A) - V(C) - { VTH }) / { RS } ) }
R1 A C 1G
*.ENDS D_IDEAL
*$
.model DIODE01 D
+ IS      = 1E-15
+ N       = 1
+ TT      = 1E-11
+ RS      = 0.5
+ CJO     = 1E-10
+ XTI     = 0.0
*$
.SUBCKT DELAY INP OUT PARAMS: RINP = 1k DELAY = 10n
R1 INP 101 {RINP}
C1 101 102 { 1.4427 * DELAY / RINP }
E1 102   0 OUT   0 0.5
E2 OUT   0 VALUE {IF(V(101) > 0.5, 1, 0)}
.ENDS DELAY
*$
.SUBCKT COMP VOUT VINP VINN PARAMS: VHYS = 0.05
E1 YINT 0 VALUE {IF(V(VINP) + V(VOUT)*VHYS > V(VINN), 1, 0)}
R1 YINT VOUT 1
C1 VOUT 0 1n
.ENDS COMP
*$
.SUBCKT COMP_INV VOUT VINP VINN PARAMS: VHYS = 0.05
E1 YINT 0 VALUE {IF(V(VINP) + (1 - V(VOUT))*VHYS > V(VINN), 0, 1)}
R1 YINT VOUT 1
C1 VOUT 0 1n
.ENDS COMP_INV
*$
.SUBCKT OP_AMP P M OUT
+ PARAMs:  Hlimit=5 Rin=10Meg BW=18Meg DC_Gain=100 Rout=100 Llimit=0 
SRP=1 SRM=1
R_Rin         P M  {Rin}
E_E1          5 0 M P {-Gain}
E_LIMIT2      6 0 VALUE {LIMIT(V(5), {-Abs(SRM)*Ca*1Meg+V(1)/Ra},
+                 {SRP*Ca*1Meg+V(1)/Ra})}
G_G2          1 0 6 0 -1
R_Ra          0 1  {Ra}
C_Ca          0 1  {Ca}
E_LIMIT1      2 0 VALUE {LIMIT(V(1),{Llimit},{Hlimit})}
V_VL          3 0 {Llimit+200m}
V_VH          4 0 {Hlimit-200m}
D_D1          3 1 Dideal
D_D2          1 4 Dideal
R_Rout        OUT 2  {Rout}
.model Dideal D Is=1e-10 Cjo=.01pF Rs=1m  N=1
.PARAM  Ra=1k   Ca={exp(DC_gain*log(10)/20)/(2*3.14159*BW*Ra)}
+ Gain={exp(DC_gain*log(10)/20)/Ra}
.ENDS OP_AMP
*$
.subckt one_shot in out params:  t=100
s_s1         meas 0 reset2 0 s1
e_abm1         ch 0 value { if( v(in)>0.5 | v(out)>0.5,1,0)    }
r_r2         reset2 reset  0.1
e_abm3         out 0 value { if( v(meas)<0.5 & v(ch)>0.5,1,0)    }
r_r1         meas ch  {t}
c_c2         0 reset2  1.4427n
c_c1         0 meas  1.4427n
e_abm2         reset 0 value { if(v(ch)<0.5,1,0)    }
.model s1 vswitch
+ roff=1e+009
+ ron=1
+ voff=0.25
+ von=0.75
.ends one_shot
*$
.SUBCKT COMPHYS2_BASIC_GEN INP INM HYS OUT PARAMS: VDD=1 VSS=0 
VTHRESH=0.5
+ T=10
EIN INP1 INM1 INP INM 1
EHYS INM2 INM1 VALUE { IF( V(1) > {VTHRESH},-V(HYS)/2,V(HYS)/2) }
EOUT OUT 0 VALUE { IF( V(INP1)>V(INM2), {VDD} ,{VSS}) }
R1 OUT 1 1
C1 1 0 {T*1e-9}
RINP1 INP1 0 10K
RINM2 INM2 0 10K
.ENDS COMPHYS2_BASIC_GEN
*$
.SUBCKT BUFFER_PS A Y PARAMS: vhi=1 vlo=0 vthresh=500e-3 tplh=1e-9
+ tphl=1e-9 tr=1e-9 tf=1e-9
RA A 0 1e11
CA A 0 0.01pF
VS VSUP 0 DC 1
EBUF1 Ypp 0 VALUE={IF(V(A) > ({vthresh}), 1, 0)}
ROUTpp Ypp 0 1e11
XNSW1 OUTp Ypp 0 NSW_PS PARAMS: RONval={(tplh+1e-15)/(1e-12*0.693)}
+ VTHval=0.5
XPSW1 OUTp Ypp VSUP PSW_PS PARAMS: RONval={(tphl+1e-15)/(1e-12*0.693)}
+ VTHval=0.5
CDEL1 OUTp 0 1pF
ETHRESH Yp 0 VALUE={IF(V(OUTp) > 0.5, 1, 0)}
ROUTp Yp 0 1e11
XNSW2 OUTr Yp 0 NSW_PS PARAMS: RONval={(tf+1e-15)/(1e-12*2.3)} 
VTHval=0.5
XPSW2 OUTr Yp VSUP PSW_PS PARAMS: RONval={(tr+1e-15)/(1e-12*2.3)} 
VTHval=0.5
CDEL2 OUTr 0 1pF
EOUT OUTf 0 VALUE={V(OUTr)*({vhi} - {vlo})+{vlo}}
RDR OUTf Y  1000
RO Y 0 1e11
.ENDS BUFFER_PS
*$
.SUBCKT INV_PS Y A PARAMS: vhi=1 vlo=0 vthresh=500e-3
+ tplh=1e-9 tphl=1e-9 tr=1e-9 tf=1e-9
RA A 0 1e11
CA A 0 0.01pF
VS VSUP 0 DC 1
EINV1 Ypp 0 VALUE={IF(V(A) > ({vthresh}), 0, 1)}
ROUTpp Ypp 0 1e11
XNSW1 OUTp Ypp 0 NSW_PS PARAMS: RONval={(tplh+1e-15)/(1e-12*0.693)}
+ VTHval=0.5
XPSW1 OUTp Ypp VSUP PSW_PS PARAMS: RONval={(tphl+1e-15)/(1e-12*0.693)}
+ VTHval=0.5
CDEL1 OUTp 0 1pF
ETHRESH Yp 0 VALUE={IF(V(OUTp) > 0.5, 1, 0)}
ROUTp Yp 0 1e11
XNSW2 OUTr Yp 0 NSW_PS PARAMS: RONval={(tf+1e-15)/(1e-12*2.3)} 
VTHval=0.5
XPSW2 OUTr Yp VSUP PSW_PS PARAMS: RONval={(tr+1e-15)/(1e-12*2.3)} 
VTHval=0.5
CDEL2 OUTr 0 1pF
EOUT OUTf 0 VALUE={V(OUTr)*({vhi} - {vlo})+{vlo}}
RDR OUTf Y  1000
RO Y 0 1e11
.ENDS INV_PS
*$
.model D_D1 d
+ is=1e-015
+ tt=10p
+ rs=0.005
+ n=0.01
*$
.model D_D2 d
+ is=1e-015
+ tt=10p
+ rs=0.005
+ n=0.001
*$
.model D_D3 d
+ is=1e-015
+ tt=10p
+ rs=0.05
+ n=0.01
*$
.SUBCKT LDCR IN OUT
+ PARAMs:  L=1u DCR=0.01 IC=0
L  IN 1  {L} IC={IC}
RDCR  1 OUT {DCR}
.ENDS LDCR
*$
.SUBCKT CESR IN OUT
+ PARAMs:  C=100u ESR=0.01 X=2 IC=0
C  IN 1  {C*X} IC={IC}
RESR  1 OUT {ESR/X}
.ENDS CESR
*$