`-i DELAY'
For bitbang-type programmers, delay for approximately DELAY
microseconds between each bit state change. If the host system is
very fast, or the target runs off a slow clock (like a 32 kHz
crystal, or the 128 kHz internal RC oscillator), this can become
necessary to satisfy the requirement that the ISP clock frequency
must not be higher than 1/4 of the CPU clock frequency. This is
implemented as a spin-loop delay to allow even for very short
delays. On Unix-style operating systems, the spin loop is
initially calibrated against a system timer, so the number of
microseconds might be rather realistic, assuming a constant system
load while AVRDUDE is running. On Win32 operating systems, a
preconfigured number of cycles per microsecond is assumed that
might be off a bit for very fast or very slow machines.
`-B BITCLOCK'
Specify the bit clock period for the JTAG interface or the ISP
clock (JTAG ICE only). The value is a floating-point number in
microseconds. The default value of the JTAG ICE results in about
1 microsecond bit clock period, suitable for target MCUs running
at 4 MHz clock and above. Unlike certain parameters in the
STK500, the JTAG ICE resets all its parameters to default values
when the programming software signs off from the ICE, so for MCUs
running at lower clock speeds, this parameter must be specified on
the command-line.