PIC24F Timer interrupt mit 4xPLL

// FBS

#pragma config BWRP = OFF    // Boot Segment Write Protect->Disabled

#pragma config BSS = OFF    // Boot segment Protect->No boot program flash segment

// FGS

#pragma config GWRP = OFF    // General Segment Write Protect->General segment may be written

#pragma config GSS0 = OFF    // General Segment Code Protect->No Protection

// FOSCSEL

#pragma config FNOSC = FRC    // Oscillator Select->FRC

#pragma config SOSCSRC = ANA    // SOSC Source Type->Analog Mode for use with crystal

#pragma config LPRCSEL = HP    // LPRC Oscillator Power and Accuracy->High Power, High Accuracy Mode

#pragma config IESO = ON    // Internal External Switch Over bit->Internal External Switchover mode enabled (Two-speed Start-up enabled)

// FOSC

#pragma config POSCMOD = NONE    // Primary Oscillator Configuration bits->Primary oscillator disabled

#pragma config OSCIOFNC = OFF    // CLKO Enable Configuration bit->CLKO output disabled

#pragma config POSCFREQ = HS    // Primary Oscillator Frequency Range Configuration bits->Primary oscillator/external clock input frequency greater than 8MHz

#pragma config SOSCSEL = SOSCHP    // SOSC Power Selection Configuration bits->Secondary Oscillator configured for high-power operation

#pragma config FCKSM = CSDCMD    // Clock Switching and Monitor Selection->Both Clock Switching and Fail-safe Clock Monitor are disabled

// FWDT

#pragma config WDTPS = PS32768    // Watchdog Timer Postscale Select bits->1:32768

#pragma config FWPSA = PR128    // WDT Prescaler bit->WDT prescaler ratio of 1:128

#pragma config FWDTEN = OFF    // Watchdog Timer Enable bits->WDT disabled in hardware; SWDTEN bit disabled

#pragma config WINDIS = OFF    // Windowed Watchdog Timer Disable bit->Standard WDT selected(windowed WDT disabled)

// FPOR

#pragma config BOREN = BOR3    // Brown-out Reset Enable bits->Brown-out Reset enabled in hardware, SBOREN bit disabled

#pragma config LVRCFG = OFF    // Low Voltage Regulator Configuration bit->Low Voltage regulator is not available

#pragma config PWRTEN = ON    // Power-up Timer Enable bit->PWRT enabled

#pragma config I2C1SEL = PRI    // Alternate I2C1 Pin Mapping bit->Use Default SCL1/SDA1 Pins For I2C1

#pragma config BORV = V20    // Brown-out Reset Voltage bits->Brown-out Reset set to lowest voltage (2.0V)

#pragma config MCLRE = ON    // MCLR Pin Enable bit->RA5 input pin disabled,MCLR pin enabled

// FICD

#pragma config ICS = PGx2    // ICD Pin Placement Select bits->EMUC/EMUD share PGC2/PGD2

// FDS

#pragma config DSWDTPS = DSWDTPSF    // Deep Sleep Watchdog Timer Postscale Select bits->1:2,147,483,648 (25.7 Days)

#pragma config DSWDTOSC = LPRC    // DSWDT Reference Clock Select bit->DSWDT uses Low Power RC Oscillator (LPRC)

#pragma config DSBOREN = ON    // Deep Sleep Zero-Power BOR Enable bit->Deep Sleep BOR enabled in Deep Sleep

#pragma config DSWDTEN = ON    // Deep Sleep Watchdog Timer Enable bit->DSWDT enabled

#define _XTAL_FREQ  32000000UL

// RCDIV FRC/1; DOZE 1:8; DOZEN disabled; ROI disabled; 

CLKDIV = 0x3000;

// TUN Center frequency; 

OSCTUN = 0x0000;

// CF no clock failure; NOSC FRCPLL; SOSCEN disabled; CLKLOCK unlocked; OSWEN Switch is Complete; 

__builtin_write_OSCCONH((uint8_t) ((0x0100 >> _OSCCON_NOSC_POSITION) & 0x00FF));

__builtin_write_OSCCONL((uint8_t) ((0x0100 | _OSCCON_OSWEN_MASK) & 0xFF));

// Wait for Clock switch to occur

while (OSCCONbits.OSWEN != 0);

IPC6bits.T4IP = 1;

//TMR4 0; 

TMR4 = 0x0000;

//Period = 1 s; Frequency = 16000000 Hz; PR4 62500; 

PR4 = 0xF424;

//TCKPS 1:256; T32 16 Bit; TON enabled; TSIDL disabled; TCS FOSC/2; TGATE disabled; 

T4CON = 0x8030;

IFS1bits.T4IF = false;

IEC1bits.T4IE = true;

/*Enable the interrupt*/

IEC1bits.T4IE = true;

/* Start the Timer */

T4CONbits.TON = 1;