1 | // FBS
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2 | #pragma config BWRP = OFF // Boot Segment Write Protect->Disabled
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3 | #pragma config BSS = OFF // Boot segment Protect->No boot program flash segment
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4 |
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5 | // FGS
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6 | #pragma config GWRP = OFF // General Segment Write Protect->General segment may be written
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7 | #pragma config GSS0 = OFF // General Segment Code Protect->No Protection
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8 |
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9 | // FOSCSEL
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10 | #pragma config FNOSC = FRC // Oscillator Select->FRC
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11 | #pragma config SOSCSRC = ANA // SOSC Source Type->Analog Mode for use with crystal
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12 | #pragma config LPRCSEL = HP // LPRC Oscillator Power and Accuracy->High Power, High Accuracy Mode
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13 | #pragma config IESO = ON // Internal External Switch Over bit->Internal External Switchover mode enabled (Two-speed Start-up enabled)
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14 |
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15 | // FOSC
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16 | #pragma config POSCMOD = NONE // Primary Oscillator Configuration bits->Primary oscillator disabled
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17 | #pragma config OSCIOFNC = OFF // CLKO Enable Configuration bit->CLKO output disabled
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18 | #pragma config POSCFREQ = HS // Primary Oscillator Frequency Range Configuration bits->Primary oscillator/external clock input frequency greater than 8MHz
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19 | #pragma config SOSCSEL = SOSCHP // SOSC Power Selection Configuration bits->Secondary Oscillator configured for high-power operation
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20 | #pragma config FCKSM = CSDCMD // Clock Switching and Monitor Selection->Both Clock Switching and Fail-safe Clock Monitor are disabled
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21 |
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22 | // FWDT
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23 | #pragma config WDTPS = PS32768 // Watchdog Timer Postscale Select bits->1:32768
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24 | #pragma config FWPSA = PR128 // WDT Prescaler bit->WDT prescaler ratio of 1:128
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25 | #pragma config FWDTEN = OFF // Watchdog Timer Enable bits->WDT disabled in hardware; SWDTEN bit disabled
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26 | #pragma config WINDIS = OFF // Windowed Watchdog Timer Disable bit->Standard WDT selected(windowed WDT disabled)
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27 |
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28 | // FPOR
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29 | #pragma config BOREN = BOR3 // Brown-out Reset Enable bits->Brown-out Reset enabled in hardware, SBOREN bit disabled
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30 | #pragma config LVRCFG = OFF // Low Voltage Regulator Configuration bit->Low Voltage regulator is not available
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31 | #pragma config PWRTEN = ON // Power-up Timer Enable bit->PWRT enabled
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32 | #pragma config I2C1SEL = PRI // Alternate I2C1 Pin Mapping bit->Use Default SCL1/SDA1 Pins For I2C1
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33 | #pragma config BORV = V20 // Brown-out Reset Voltage bits->Brown-out Reset set to lowest voltage (2.0V)
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34 | #pragma config MCLRE = ON // MCLR Pin Enable bit->RA5 input pin disabled,MCLR pin enabled
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35 |
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36 | // FICD
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37 | #pragma config ICS = PGx2 // ICD Pin Placement Select bits->EMUC/EMUD share PGC2/PGD2
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38 |
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39 | // FDS
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40 | #pragma config DSWDTPS = DSWDTPSF // Deep Sleep Watchdog Timer Postscale Select bits->1:2,147,483,648 (25.7 Days)
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41 | #pragma config DSWDTOSC = LPRC // DSWDT Reference Clock Select bit->DSWDT uses Low Power RC Oscillator (LPRC)
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42 | #pragma config DSBOREN = ON // Deep Sleep Zero-Power BOR Enable bit->Deep Sleep BOR enabled in Deep Sleep
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43 | #pragma config DSWDTEN = ON // Deep Sleep Watchdog Timer Enable bit->DSWDT enabled
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44 |
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45 |
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46 |
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47 | #define _XTAL_FREQ 32000000UL
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48 |
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49 | // RCDIV FRC/1; DOZE 1:8; DOZEN disabled; ROI disabled;
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50 | CLKDIV = 0x3000;
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51 | // TUN Center frequency;
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52 | OSCTUN = 0x0000;
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53 | // CF no clock failure; NOSC FRCPLL; SOSCEN disabled; CLKLOCK unlocked; OSWEN Switch is Complete;
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54 | __builtin_write_OSCCONH((uint8_t) ((0x0100 >> _OSCCON_NOSC_POSITION) & 0x00FF));
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55 | __builtin_write_OSCCONL((uint8_t) ((0x0100 | _OSCCON_OSWEN_MASK) & 0xFF));
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56 | // Wait for Clock switch to occur
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57 | while (OSCCONbits.OSWEN != 0);
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58 |
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59 | IPC6bits.T4IP = 1;
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60 |
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61 | //TMR4 0;
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62 | TMR4 = 0x0000;
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63 | //Period = 1 s; Frequency = 16000000 Hz; PR4 62500;
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64 | PR4 = 0xF424;
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65 | //TCKPS 1:256; T32 16 Bit; TON enabled; TSIDL disabled; TCS FOSC/2; TGATE disabled;
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66 | T4CON = 0x8030;
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67 |
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68 |
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69 | IFS1bits.T4IF = false;
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70 | IEC1bits.T4IE = true;
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71 |
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72 |
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73 | /*Enable the interrupt*/
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74 | IEC1bits.T4IE = true;
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75 |
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76 | /* Start the Timer */
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77 | T4CONbits.TON = 1;
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