Suchergebnisse für "when others"

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3880 Treffer für when others Suchergebnisse für "when others"

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  • Datei

    AudioInterface.vhd

    reg_ready_f : out std_logic ); end component; signal s_delay : std_logic_vector(11 downto 0) := (others => '0'); signal s_filter_input_data_l_16_bit : std_logic_vector(15 downto 0) := (others => '0'); signal s_filter_input_data_r_16_bit : std_logic_vector(15 downto 0) := (others => '0'); signal s_filtered_output_data_l

    in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·

  • Datei

    top_gesamt.vhd

    Adresse, 00 bei Einzelansteuerung 11 bei alle Kanäle gleich dac_input(17 downto 16) <= adr; case adr is when "00" => dac_input(15 downto 0) <= data0; when "01" => dac_input(15 downto 0) <= data1; when "10" => dac_input(15 downto 0) <= data2; when "11" => dac_input(15 downto 0) <= data3; when others => dac_input(15 downto 0) <= (others => '0'); end case; elsif rising_edge(clk) then dac_input <= dac_input(22 downto 0) & '0'; -- serielle Ausgabe end if; dac_sdi <= dac_input(23); -- Ausgabe auf Datenleitung end process; end Behavioral

    in „Schaltung passt nicht in CPLD“ · FPGA, VHDL & Co. ·

  • Datei

    fsm_3process.vhd

    ; end if; end process; output_decode : process(state,ain,reset) begin yout <= '0'; case(state) is when S0 => if reset = '0' then if ain = '1' then yout <= '1'; else yout <= '0'; end if; end if; when S1 => yout <= '0'; when S2 => yout <= '0'; when others => yout <= '0'; end case; end process; count <=

    in „Probleme bei Vivado Tutorial mit State Machine“ · FPGA, VHDL & Co. ·

  • Datei

    ddr.vhd

    -------- when Precharge0 => ic.cmd <= CMD_PRECHARGE; ic.adr(10) <= '1'; -- Precharge all operation. iin.s <= Precharge0Wait; -- PRECHARGE command period tRP: 15ns when Precharge0Wait => if i.c = 1 then iin.c <= 0

    in „Spartan-3E Starter Kit + DDR2“ · FPGA, VHDL & Co. ·

  • Thread

    fehlende Testbench Befehle

    5000 [/pre] [vhdl] : constant time_unit : time := 1 us; : read(line, mark); case mark is when '#' => null; -- ignore comments when 'T' => read(line, space); read(line, time_value); wait for time_value * time_unit; : when others => null; end case; [/vhdl]

    signal testbench_clock : std_logic := '0'; : testbench_clock <= not testbench_clock after period/2 when simulation_active; : process begin : -- apply some test vectors : simulation_active <= false; wait; end process; [/vhdl] Duke

    FPGA, VHDL & Co. ·Martin · ·12 Antworten

  • Thread

    Schleifen untile oder while

    ein kleines Beispiel? process(clk) begin if rising_edge(clk) then case state is when warten => if taste='1' then state = Z1; end if; when z1 => state = Z2; when z2 => if code="111" then

    else state <= Z1; end if; when others => state <= warten; end case; end if; end process; Das Beispiel ist zwar wenig sinnvoll, zeigt aber das Prinzip. >Die Tasten sind in dem programm schon entprellt worden. Welchem

    FPGA, VHDL & Co. ·Bernd · ·12 Antworten

  • Datei

    FIRFilter.vhd

    - 1) of std_logic_vector(3 * DSIZE - 1 downto 0); -- 48 Bit Akkumulator signal a_sop : ASOP := ( others => x"000000000000" ); type ACOEF is array (0 to NBTAP - 1) of std_logic_vector(0 to DSIZE - 1); signal a_coeff : ACOEF := ( others => x"0000" ); begin blk_mem_gen : blk_mem_gen_0 PORT MAP ( clka =>

    in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·

  • Thread

    Internen Oszillator aktivieren

    <= '0'; ce <= '0'; error <= '1'; when "0100" => up_down <= '0'; ce <= '1'; error <= '0'; when "0101" => up_down <= '0'; ce <= '0'; error <= '0'; when "0110" => up_down <= '0'; ce <= '0'; error <= '1'; when "0111" => up_down

    <= '0'; ce <= '0'; error <= '0'; when others => null; end case; end process; end Behavioral;[/vhdl]

    FPGA, VHDL & Co. ·Michael H. · ·25 Antworten

  • Thread

    Ampelschaltung

    CNTPHASE <= TREDAMBER; when REDAMBER => STATE <= GREEN; CNTPHASE <= TGREEN; when GREEN => STATE <= AMBER;

    DUTYPEDR <= "00000000"; end if; -- Pedestrian light OFF when others => DUTYMAINR <= "10000000"; DUTYMAING <= "00000000"; DUTYSIDER <= "10000000"; DUTYSIDEG <= "00000000";

    FPGA, VHDL & Co. ·Moritz R. · ·40 Antworten

  • Datei

    i2s_data_interface.vhd

    architecture Behavioral of i2s_data_interface is -- signal bit_counter : unsigned(5 downto 0) := (others => '0'); -- todo rausgenommen 22_07_2020 signal bclk_delay : std_logic_vector(9 downto 0) := (others => '0'); signal lr_delay : std_logic_vector(9 downto 0) := (others => '0'); signal sr_in : std_logic_vector(126 downto 0) := (others => '0'); signal sr_out : std_logic_vector(63 downto 0) := (others => '0'); signal i2s_lr_last : std_logic := '0'; signal i2s_d_in_last : std_logic := '0'; begin process(clk) begin -- Process to predict

    in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·

  • Datei

    Neues_Textdokument__6_.txt

    SYNC <= '0'; end if; if (( bit_count >= 0) and (bit_count <= 15)) then --Slot0-Tag case bit_count is when 0 => AC97_SDATA_OUT <= '1'; when 1 => AC97_SDATA_OUT <= '1'; when 2 => AC97_SDATA_OUT <= '1'; when others => AC97_SDATA_OUT <= '0'; end case; elsif (( bit_count >= 16) and (bit_count <= 35)) then AC97

    in „ISE-WebPack: iSim stoppt ungewollt die Simulation“ · FPGA, VHDL & Co. ·

  • Datei

    fifo_dc.vhd

    i_wr_clk, i_reset) begin if i_reset = '1' then s_write_reset_done <= '0'; s_read_reset_done_sr <= (others => '0'); s_wp_bin_wcd <= (others => '0'); s_rp_gray_wcd <= (others => '0'); else if rising_edge(i_wr_clk) then s_write_reset_done <= '1'; s_read_reset_done_sr <= s_read_reset_done_sr(0) & s_read_reset_done

    in „Xilinx Spartan 3 xc3s400 FIFO mit hoher Frequenz“ · FPGA, VHDL & Co. ·

  • Datei

    log_rom.vhd

    "00000101" => dout <= "000001110"; when "00000110" => dout <= "000010001"; when "00000111" => dout <= "000010100"; when "00001000" => dout <= "000010111"; when "00001001" => dout <= "000011010"; when "00001010" => dout <= "000011100"; when

    in „Logarithmus in VHDL“ · FPGA, VHDL & Co. ·

  • Thread

    Function Aufruf ergibt Fehler. Warum?

    aufgerufen werden. [vhdl] begin ..... if (MASTER = x"00") then case WERT_TT is when TT_0 => WERT_R_16BIT_OUT <= (others => '0'); WERT_R_16BIT_OUT <= (others => '0'); when TT_1 => WERT_R_16BIT_OUT <= SCALING(WERT_R_16BIT_IN); WERT_R_16BIT_OUT <

    FPGA, VHDL & Co. ·Marco · ·2 Antworten

  • Thread

    Frequenzteiler

    when "00011" => cnt_div <= 8-1; -- 3 | 10Mhz | 2µs when "00100" => cnt_div <= 20-1; -- 4 | 4Mhz | 5µs when "00101" => cnt_div <= 40-1; -- 5 | 2Mhz | 10µs

    when "10101" => cnt_div <= 8000000-1; -- 21 | 10 hz | 2 s when "10110" => cnt_div <= 20000000-1; -- 22 | 4 hz | 5 s when others => end case; else if cnt = cnt_div

    FPGA, VHDL & Co. ·M. N. · ·22 Antworten

  • Thread

    seriell-parallel Umsetzer mit EPM3032

    begin -- der Zähler process (sclk,cs) begin if (cs = '0') then lpm_cnt <= (others=>'0'); elsif rising_edge(sclk) then if (cs='1') then lpm_cnt <= std_logic_vector(unsigned(lpm_cnt) + 1); end if; end if; end process; -- das

    sdata; end if; end if; end process; -- ein Latch do <= "00000000" when cs = '0' else lpm_sr when lpm_cnt(2 downto 0) = "111" else do; -- ein wenig Kombinatorik nwe <= '1' when lpm_cnt(2 downto 0) = "111" else '0';

    FPGA, VHDL & Co. ·Anfänger · ·35 Antworten

  • Thread

    VHDL - Initialwerte/State machine

    if rising_edge(CLKO) then LED_PWR_GOOD <= not LED_PWR_GOOD; case state is when init1 => LED_TEST_GOOD <= '0'; state <= test1; when test1 => LED_TEST_GOOD <= '1'; state <= init2; when init2 => LED_TEST_GOOD <= '0'; state <= test2; when test2 => LED_TEST_GOOD <= '1'; state <= init1; when others => state <= init1; end case; end if; end process; M0 <= not LED_PWR_GOOD;

    FPGA, VHDL & Co. ·Peter Krause · ·8 Antworten

  • Datei

    UART.vhd

    STD_LOGIC := '0'; BEGIN PROCESS (CLK) IS BEGIN IF RISING_EDGE(CLK) AND CE='1' THEN CASE RX_BIT_COUNT IS WHEN 0 => IF(RX='0')THEN RX_BIT_COUNT <= 1; END IF; WHEN 9 => RX_BIT_COUNT <= 0; OUTP <= OUT_BUF; WHEN OTHERS => RX_BIT_COUNT <= RX_BIT_COUNT + 1; OUT_BUF <= RX & OUT_BUF(7 downto 1); END CASE; END IF; END PROCESS; PROCESS (CLK) IS BEGIN IF RISING_EDGE(CLK) AND CE='1' THEN CASE TX_BIT_COUNT IS WHEN 0 => IF(SEND_BUF='0' AND SEND='1')THEN TX_BIT_COUNT <= 1; TX <= '0'; ELSE TX <= '1'; END IF; SEND_BUF <= SEND; WHEN 9 => TX <= '1'; TX_BIT_COUNT <= 0; WHEN OTHERS => TX <= DATA(TX_BIT_COUNT-1); TX_BIT_COUNT

    in „Arbeiten mit RS 232“ · Mikrocontroller und Digitale Elektronik ·

  • Thread

    Klausurvorbereitung Digitaltechnik (VHDL)

    Altklausuren oft über einen Ausdruck gestolpert, den > ich nicht richtig zu interpretieren weiß: > > WHEN ("100" XOR "001") => w<='0'; Ist gleichbedeutend zu [vhdl] WHEN "101" => w <='0'; [/vhdl] > 2. VHDL selber schreiben in Bezug auf synchrone Schaltwerke: > Ich habe ein Zustandsdiagramm

    ist - beides passt hier aber y wäre --dann y=100 [...] weiter unten das gleiche Spiel [...] WHEN OTHERS => y<="111"; --Bezug auf obige case Anweisung, noch im Process IF x(1) ='1' THEN IF x(0)='0 THEN z<=za; --also x=10 und y=111 ELSE z<=zb; y(1) <= '0'; END IF;

    FPGA, VHDL & Co. ·Skyscraper91 · ·11 Antworten

  • Thread

    INFO:Xst:2117 wie "add an 'INIT' attribute" zu state?

    '; next_state <= WAIT_ENABLE; case current_state is when WAIT_ENABLE => if READ_ENABLE = '1' then next_state <= WAIT_WINDOW_START; end if; when WAIT_WINDOW_START =>

    next_state <= WAIT_ENABLE; when others => next_state <= WAIT_ENABLE; end case; end process; [/vhdl] In diesem Fred ging es ums gleiche Thema: http://www.mikrocontroller.net/topic/50173#new Demzufolge

    FPGA, VHDL & Co. ·Martin Kohler · ·9 Antworten

  • Datei

    i2s_data_interface.vhd

    architecture Behavioral of i2s_data_interface is -- signal bit_counter : unsigned(5 downto 0) := (others => '0'); -- todo rausgenommen 22_07_2020 signal bclk_delay : std_logic_vector(9 downto 0) := (others => '0'); signal lr_delay : std_logic_vector(9 downto 0) := (others => '0'); signal sr_in : std_logic_vector(126 downto 0) := (others => '0'); signal sr_out : std_logic_vector(63 downto 0) := (others => '0'); signal i2s_lr_last : std_logic := '0'; signal i2s_d_in_last : std_logic := '0'; begin process(clk) begin -- Process to predict

    in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·

  • Datei

    i2s_data_interface.vhd

    architecture Behavioral of i2s_data_interface is -- signal bit_counter : unsigned(5 downto 0) := (others => '0'); -- todo rausgenommen 22_07_2020 signal bclk_delay : std_logic_vector(9 downto 0) := (others => '0'); signal lr_delay : std_logic_vector(9 downto 0) := (others => '0'); signal sr_in : std_logic_vector(126 downto 0) := (others => '0'); signal sr_out : std_logic_vector(63 downto 0) := (others => '0'); signal i2s_lr_last : std_logic := '0'; signal i2s_d_in_last : std_logic := '0'; begin process(clk) begin -- Process to predict

    in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·

  • Datei

    i2s_data_interface.vhd

    architecture Behavioral of i2s_data_interface is -- signal bit_counter : unsigned(5 downto 0) := (others => '0'); -- todo rausgenommen 22_07_2020 signal bclk_delay : std_logic_vector(9 downto 0) := (others => '0'); signal lr_delay : std_logic_vector(9 downto 0) := (others => '0'); signal sr_in : std_logic_vector(126 downto 0) := (others => '0'); signal sr_out : std_logic_vector(63 downto 0) := (others => '0'); signal i2s_lr_last : std_logic := '0'; signal i2s_d_in_last : std_logic := '0'; begin process(clk) begin -- Process to predict

    in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·

  • Datei

    i2s_data_interface.vhd

    architecture Behavioral of i2s_data_interface is -- signal bit_counter : unsigned(5 downto 0) := (others => '0'); -- todo rausgenommen 22_07_2020 signal bclk_delay : std_logic_vector(9 downto 0) := (others => '0'); signal lr_delay : std_logic_vector(9 downto 0) := (others => '0'); signal sr_in : std_logic_vector(126 downto 0) := (others => '0'); signal sr_out : std_logic_vector(63 downto 0) := (others => '0'); signal i2s_lr_last : std_logic := '0'; signal i2s_d_in_last : std_logic := '0'; begin process(clk) begin -- Process to predict

    in „Genesys 2 (Xilinx Kintex 7): Audio-Codec Implementierung und Filteranbindung“ · FPGA, VHDL & Co. ·

  • Datei

    mii_inout.vhd

    = '1' then rxstate <= idle; rx_buffer <= (others => '0'); elsif rising_edge(clk100) and (rxclk_sync = '0') then rx_stb_o <= '0'; frame_start <= '0'; case rxstate is when idle => if rxdv = '1' then rxstate <= wa; rx_buffer <= (others => '0'); end if; when wa => rxstate <= data_lo; when data_lo => frame_start <= '1'; if rxdv = '0' then rxstate <= idle; else rx_buffer(7 downto 4) <= rxd; rxstate <= data_hi; end if; when data_hi => frame_start <= '1'; if

    in „Ethernet Pakete empfangen(MII)“ · FPGA, VHDL & Co. ·

  • Thread

    Altera Timequest signal als clock identifiziert

    if v_counter=0 then v_counter := CLK_MUL-1; case l_mstate is when IDLE => null; l_mstate <= IDLE; --set the machine to start. when START => l_obit <= '0'; l_mstate <= SEND; v_bcnt

    vcnt_stbbit := vcnt_stbbit-1; end if; when others => l_mstate <= IDLE; end case; else v_counter := v_counter - 1; end if; end if; end if; end process P1; PO: process(l_obit,l_ready)

    FPGA, VHDL & Co. ·MALGUCKEN · ·26 Antworten

  • Datei

    counter.txt

    std_logic_vector (3 downto 0); begin if (DIR='1') then -- construction of a look-up-table for the next state when counting up case count is when "1001" => next_state<="0000"; when others => next_state<=count+1; end case; end if; if (DIR='0') then -- construction of a look-up-table for the next state when counting down case count is when "0000" => next_state<="1001"; when others => next_state<=count-1; end case; end if; if ((RESET and DIR)='1') then -- Reset has the first priority count:="0000"; elsif (RESET='1' and DIR='0') then count

    in „bad synchronous description“ · FPGA, VHDL & Co. ·

  • Thread

    VHDL Case statement covers only 4 out of 81 cases.

    4 Möglichkeiten und nicht 86! CASE instruction_register( 15 DOWNTO 14 ) is when "00" => linear_address <= DPP0(3 downto 0)&(instruction_register( 13 DOWNTO 0 )); when "01" => linear_address <= DPP1(3 downto 0)&(instruction_register( 13 DOWNTO 0 )); when "10" => linear_address

    Man sollte immer auch ein "when others" hinzufügen, auch wenn es eigendlich überflüssig ist, dann passiert das nicht. Du musst bedenken, dass man bei den erweiteren Signaltypen nicht nur mit 0 und 1 arbeitet, sondern auch mit undefinierten

    FPGA, VHDL & Co. ·123 · ·4 Antworten

  • Thread

    clocks in lattice ecp2

    Hallo, wenn ich die Zeile led_out(0) <= '1' when Kanal_1 < pwm0 else '0'; auskommentiere, komm ich laut Trace Report auf 264MHz... Hab dann nur mehr eine 24MHz Clock, clk_pwm wird in der portmap vom pwm module auf clk_100 verdrahtet

    Hallo, habe das jetzt ausprobiert: led_temp <= '1' when Kanal_1 < pwm0 else '0'; process (clk_pwm) begin if rising_edge(clk_pwm) then led_register <= led_temp; end if; end process; led_out(0) <= led_register

    FPGA, VHDL & Co. ·Bernhard P. · ·11 Antworten

  • Thread

    CPLD defekt?

    trigger1 <= '1'; Mode <= "0111"; end if; when "0111" => -- WE on '1'; counter <= to_X01(counter + 1); Mode <= "0000"; when "1000" => --

    counter + 1); OE <= '0' after 20 ns, '1' after 60 ns; when OTHERS => Mode <= Mode; end case; end if; end if; end process; clock_source : process(clk_1, clk_2, clk_src) begin if (clk_src = '1') then clk <= clk_1; else

    FPGA, VHDL & Co. ·Jojo · ·11 Antworten

  • Thread

    Idee für universeller Decoder VHDL Code?

    architecture RTL of DECODE_Xto1 is begin process (SEL, SIG_IN) begin case SEL is when "000" => SIG_OUT <= SIG_IN(0); when "001" => SIG_OUT <= SIG_IN(1); when "010" => SIG_OUT <= SIG_IN(2); when "011" => SIG_OUT <= SIG_IN(3); when "100" => SIG_OUT <= SIG_IN(4); when "101" => SIG_OUT <= SIG_IN(5); when "110" => SIG_OUT <= SIG_IN(6); when "111" => SIG_OUT <= SIG_IN(7); -- For simulation only when others => SIG_OUT <= 'X';

    FPGA, VHDL & Co. ·Max Müller · ·2 Antworten

  • Thread

    Transistortester AVR

    can you add please on makefile an option to compensate the voltage drop of the protection diode when misure the battery voltage ?

    Hi Karl, i've added an external 2,5V reference to pd4 and i see 5.04v when i push the test button. Is that a good value ?

    Projekte & Code ·Karl-Heinz Kübbeler · ·6487 Antworten

  • Datei

    i2c_slave_model.vhd

    = 'd'; when "1110" => result := 'e'; when "1111" => result := 'f'; when others => result := 'x'; end case; return result; end; -- converts slv byte to two char hex-string function slv8_xstr (inp: STD_LOGIC_VECTOR

    in „Probleme bei Lattice I2C EFB mit Wishbone Interface“ · FPGA, VHDL & Co. ·

  • Thread

    Probleme bei der Umstellung von Verilog nach VHDL

    when "0010" => mmc_doreg <= mmc_mosi_reg(5); when "0011" => mmc_doreg <= mmc_mosi_reg(4);

    when "0110" => mmc_doreg <= mmc_mosi_reg(1); when others => mmc_doreg <= mmc_mosi_reg(0);

    FPGA, VHDL & Co. ·Michael Fischer · ·18 Antworten

  • PDF

    einf__hrung_in_vhdl.pdf

    Auswahlwer- te nicht den kompletten Wertebereich ab, so muß in der letzten Alternative der Auswahlwert others verwendet werden, der alle noch nicht aufgeführten Auswahlwerte beinhaltet. Beispiel: case Kalendertag is -- Wertebereich von Kalendertag sei 1 bis 31 when 1 | 16 => Anweisungen für 1 und 16 ; when 2 => Anweisungen für 2 ; when 7 to 15 => Anweisungen für 7 bis 15 ; when others => Anweisungen für 3 bis 6 und 17 bis 31 ; end case; 2.4.4 Loop Anweisung in VHDL lassen sich unendliche Schleifen, sogenannte While-Schleifen und sogenannte

    in „Erste Schritte mit FPGA - ich komme nicht weiter“ · FPGA, VHDL & Co. ·

  • Thread

    ALLPOWERS S2000 PRO Reparaturhilfe

    when i use j flash lite, everything goes ok with no errors, but when i read the flash, it's the old one, not the one i have just flased into it :(

    shows 100% battery, the car port is flashing, the power button does not work as a power button, but when you hold it, it turns on the bluetooth, the ac button works but when you turn it on it pull up error 303 e0303 and shuts off but there is 220v at the output and you can't turn it off.... after few hours

    Mikrocontroller und Digitale Elektronik ·Kai B. · ·270 Antworten

  • Thread

    Flipflop auf rising und falling edge triggern (XC9572XL)

    failed" severity error; -- fullcycle 1: read reset vector from 0x000000 to 0x000007 (SP + PC) when OVL_LOCAL is 1: reads from flash wait until fullcycle'event; A <= (others => 'U'), x"00" after speriod * 1.5, (others => 'U') after speriod * 8.0; ALOW <= (others => 'U'), x"0

    = '1', '0' after speriod * 2.5, '1' after speriod * 7.1; D <= (others => 'U'), x"00" after speriod * 6.5, (others => 'U') after speriod * 8.0; wait for speriod * 0.75; assert (nOVR='Z') report "nOVR failed" severity error; assert (nDTACK='Z') report

    FPGA, VHDL & Co. ·Michael D. · ·22 Antworten

  • Datei

    prog.txt

    others => Wert_Druck_Vorwahl<="000000000000"; end case; -- Aufnahme Wert Feuchtevorwahl case S5 is when "001" => Wert_Feuchte_Vorwahl<="000000000010"; when "010" => Wert_Feuchte_Vorwahl<="000000000100"; when "011" => Wert_Feuchte_Vorwahl<="000000001000"; when "100" => Wert_Feuchte_Vorwahl<="000000010000"; when others => Wert_Feuchte_Vorwahl<="111111111111"; end case; ----------------------------------------------------------------------------------------

    in „Betriebsblind“ · FPGA, VHDL & Co. ·

  • Thread

    VHDL/DCM für Spartan-3E

    process(clk) begin if (clk'event and clk ='1') then case sw is when "0000" => led <= "00000000"; when "1111" => led <= "10000001"; when "0001" => led <= "11111111"; when "0010" => led <= "01010101"; when "0100" => led <= "11001100"; when "1000" => led <= "00110011"; when others => end case; end if; end process output_ports; end Behavioral;

    FPGA, VHDL & Co. ·jo_weber · ·12 Antworten

  • Thread

    Frage zur DDFS von Lothar Miller

    Data_sin2 <= Result_sin2; when "00" => Result_sin2 <= Sinus_Rom ( to_integer(Address)); Data_sin2 <= std_logic_vector (-signed(Result_sin2)); when "01" => Result_sin2 <= Sinus_Rom (63-to_integer(Address)); Data_sin2 <= std_logic_vector (-signed(Result_sin2)); when others => null; end case; [/vhdl] das gleiche ist. Die Simulationsergebnisse haben aber einen kleinen Unterschied. Bei der case-Variante bekomme ich, sobald die Adresse 1 wird, immer komische

    FPGA, VHDL & Co. ·Michael · ·22 Antworten

  • PDF

    INR-18650.pdf

    test 9.2 External short-circuit test 9.3 Reverse charge test 9.4 Heating test 10.0. Warranty 11.0. Others 11.1 Storage for a long time 11.2 Others 12.0. Packing Proper use and handling of lithium ion cells Handling precaution and prohibitions of lithium Ion rechargeable cells and batteries Samsung SDI

    in „LIOH austauschbar ?“ · Analoge Elektronik und Schaltungstechnik ·

  • PDF

    SAMSUNG_INR18650-25R.pdf

    test 9.2 External short-circuit test 9.3 Reverse charge test 9.4 Heating test 10.0. Warranty 11.0. Others 11.1 Storage for a long time 11.2 Others 12.0. Packing Proper use and handling of lithium ion cells Handling precaution and prohibitions of lithium Ion rechargeable cells and batteries Samsung SDI

    in „Li Ion 18650 Brandgefahr“ · Offtopic ·

  • Thread

    KiCAD - Bibliotheken zusammenführen - wie geht das ?

    Die beiläufige Erwähnung des "library cache" im KiCad Getting-Started ist auch nicht erhellend: "When you share a project, you should at least keep the library cache (-cache.lib) with it, to ensure that others can see your symbols" Lässt sich das Anlegen eines Library-Caches verhindern - will man

    beiläufige Erwähnung des "library cache" im KiCad Getting-Started > ist auch nicht erhellend: "When you share a project, you should at least > keep the library cache (-cache.lib) with it, to ensure that others can > see your symbols" Ist weiter oben in diesem Post erklärt. ;O) > > Lässt

    Platinen ·Andreas R. · ·7 Antworten

  • Thread

    Hamming Coder

    könnte es also ganz ohne jeglichen Prozess so schreiben: [vhdl] with A select K <= "0111" when "00000", "0011" when "00001", "1001" when "00011", : : "1111" when "11101", "1001" when "11110", "1101" when others; -- "11111" [/vhdl] Und wenn

    FPGA, VHDL & Co. ·Kevin Rosa · ·4 Antworten

  • Thread

    Source Files zu Hexcode wandeln geht nicht

    Init: On during Init * Status LED Ready: Flashing when Idle * Status LED Gate Open: On when the Gate is Open * ******************************************************************************* * The Phone has to support the following Commands: *

    Init_Chip (void) { // Port B: // Bit 4 = Input // Others = Output DDRB = 0xEF; // DDR Port B: 1110 1111 PORTB = 0; // Init LED ON // Port D: // Bit 0 = Input // Others = Output DDRD = 0xFF;

    Mikrocontroller und Digitale Elektronik ·Andreas Lechner · ·10 Antworten

  • Datei

    uart_tx.vhd

    architecture RTL of uart_tx is signal enable : std_logic := '0'; signal txbaud : unsigned(19 downto 0) := (others => '0'); signal txdata : std_logic_vector(9 downto 0) := "1000000000"; signal tick : std_logic := '0'; signal tickcnt : unsigned(19 downto 0) := (others => '0'); signal bitcnt : integer range 0 to

    in „UART-Empfänger verliert Sync“ · FPGA, VHDL & Co. ·

  • Datei

    data_receiver.vhd

    = '1'; when "111" => rx_filt <= '1'; when others => null; end case; end process; -- bit timing counter process(clk) begin if rising_edge(clk) then if ce='1' then if rx_smp(2 downto 1) = "10" and state=idle then

    in „datenübertragung: clk dividieren“ · FPGA, VHDL & Co. ·

  • Datei

    wb_sm_async_bridge.vhd

    s_exit_without_ack <= false; wb_cyc_o <= '0'; wb_stb_o <= '0'; s_dsp_ardy <= '0'; wb_we_o <= '0'; wb_sel_o <= (others => '1'); wb_dat_o <= (others => '0'); else case s_wb_bridge_states is when wait_for_dsp_access_state => s_dsp_ardy <= '0'; if s_dsp_ams_n_sync = '0' then -- active memory select from dsp wb_adr_o <

    in „Hilfe bei timing constraints für asynchrones Interface zu Blackfin DSP“ · FPGA, VHDL & Co. ·

  • Datei

    TLC.txt

    stateD; i<=0; else i<=i+1; end if; when stateD=> if(i=100000000) then state <= stateA; i<=0; else i<=i+1; end if; end case; end if; end process; with State select T <= '0' when stateA|stateC, '1' when others; end Behavioral; #############

    in „Trafic-Lights-Controller, Clk Problem“ · FPGA, VHDL & Co. ·

  • Thread

    Xilinx Spartan 3AN -- DDR2 SDRAM Ansteuerung

    auf Grundlage der UCF-Datei ist: [vhdl] SD_A : in std_logic_vector(15 downto 0) := (others => '0'); SD_BA : in std_logic_vector(2 downto 0) := (others => '0'); SD_RAS : in std_logic := '0'; SD_CAS : in std_logic := '0'; SD_CK_N : in std_logic := '0'; SD_CK_P :

    <= counter - 1; end if; when RECEIVE => command_register <= "000"; if init_done = '1' then --and falling_edge(clk_i) then command_register <= "100"; input_adress <= "0000000000000000000000000

    FPGA, VHDL & Co. ·Frank S. · ·77 Antworten