at 27.125MHz 8. According to TIA-603-C, typical values measured at 462.5625MHz, maximum value measured at 27.125MHz 9. AF FREQ 300Hz, AF Deviation 3kHz. Measured on 8Ohm speaker 10.-50dBm RF input power
MAX UNIT D package 1.5 Mounted on JEDEC 4-layer board (JESD 51-7), PD Power dissipation No airflow,AT = 25°CJ T = 125°C N package 1 W PW package 0.9 D package 103 Mounted on JEDEC 1-layer board (JESD 51-3), No airflow N package 148 PW package 176 θJA Thermal impedance, °C/W junction to free air D package
MAX UNIT D package 1.5 Mounted on JEDEC 4-layer board (JESD 51-7), PD Power dissipation No airflow,AT = 25°CJ T = 125°C N package 1 W PW package 0.9 D package 103 Mounted on JEDEC 1-layer board (JESD 51-3), No airflow N package 148 PW package 176 θJA Thermal impedance, °C/W junction to free air D package
capture registers 0 to 7 (REGMODEn bit = 1) These registers allow software to read the counter values at which the event selected by the corresponding Capture Control registers occurred. Table 256. SCT capture registers 0 to 7 (CAP[0:7], address 0x1C02 0100 (CAP0) to 0x1C02 011C (CAP7) (SCT2) and address 0x1C02 4100 (CAP0) to 0x1C02 411C (CAP7) (SCT3)) bit description (REGMODEn bit = 1) Bit Symbol Description Reset value 15:0 CAPn_L When UNIFY = 0, read the 16-bit counter value at which this 0 register was
copied from the BIOS ROM to system RAM for faster execution. The setting is either Enabled or Disabled. C000,16K Shadow C400,16K Shadow These options specify how the 32 KB of video ROM at C0000h is treated. The settings are: Enabled (default), Disabled and Cached. C800,16K Shadow CC00,16K Shadow D000,16K
I C slave mode The peripheral input clock must be programmed in the I2C_FREQR register in order to generate correct timings. The peripheral input clock frequency must be at least: 1 MHz in Standard mode
two channels 250kbps 23 mA VDD IVDD Supply current two channels 1000kbps 25 mA RX SENS Sensitivity at 0.1%BER (@250kbps) -90 dBm RX SENS Sensitivity at 0.1%BER (@1000kbps) -80 dBm C/ICO Cst Co-channel 8) 10/4 dB C/I1ST 1 Adjacent Channel Selectivity C/I 1MHz 8) -20/0 dB C/I2ND 2 Adjacent Channel Selectivity
PayPal (Kosten tragt ihr). Anfragen zum Kauf bitte per Mail oder PN und *nicht* ins Forum: bauteile ät lostemp punkt de Diskussionen und Fragen zu Bauteilen können natürlich im Forum gestellt werden. ---------- *LEDs* ---------- *Flächen-LEDs* - gelb, grün oder rot: 10x10 mm, 20mA, THT 2,5 mm
Moin, ich wurde grade darauf hingewiesen, dass die 24LC01B nur 128 Byte Speicher haben (statt 256 Byte wie bisher beschrieben). Habe es oben in der Liste korrigiert. Die betroffenen Käufer haben ne Mail.
1-MHz tolerance overall DCOCTL = CALDCO_1MHZ, -40°C to 85°C 1.8 V to 3.6 V -6 ±3 +6 % calibrated at 30°C and 3 V BCSCTL1= CALBC1_8MHZ, 8-MHz tole(1)ce over DCOCTL = CALDCO_8MHZ, 0°C to 85°C 3 V -3 ±0.5 +3 % temperature calibrated at 30°C and 3 V BCSCTL1
Range b) 24AA32A-I/SN: Industrial Temperature,1.8V, 2 SOIC package Device: 24AA32A: 1.8V, 32 Kbit 2 C Serial EEPROM c) 24AA32A-I/SM: Industrial Temperature.,1.8V, 24AA32AT: 1.8V, 32 Kbit I C Serial EEPROM SOIC (208 mil) package (Tape and Reel) 24AA32AX 1.8V, 32 Kbit I 2C Serial EEPROM in d) 24AA32AX-I
The history of the NXP Hitag2 family of transpon- munication can be intercepted over a distance of at least ders overlaps with that of other security products de- 100 meters. signed and deployed in the late nineties, such as Kee- 1http://www.nxp.com/products/automotive/ loq [ 8, 13, 27, 28], MIFARE Classic
bi-directional devices hRving V volts and underR the I limit is doubled. DS21503 Rev. 10 - 2 2 of 4 1.5KE6V8(C)A - 1.5KE400(C)A www.diodes.com 10,000 )p Ip Measured at ( 100 Peak Valpp I Zero Bias T F N ( R E R C 1000 U A C Half Valpp I /2 I S A L P U 50 C Measured at P ,T Stand-off Voltage A C E 100 , IP t p
TCM8240MD Ver 1.3 2 TOSHIBA C MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC Ver 1.3 15/Apr/04 TCM8240MD TENTATIVE 1.3 Mega pixel sensor chip TCM8240MD is an area color image sensor , at 1.3 Mega-pixels of array resolution (1300x
jetzt ist, wirst Du nicht glücklich, das garantiere ich Dir. Der nächstgrößere CHip ist der PIC32MX250F256H (B:28 Pins, C: 36 Pins, D: 44/48 Pins, H:64 Pin, L:100 Pins) 5. keine Eingänge an den Levelshiftern offen lassen 6. Reset vom WDC softwaremäßig ansteuerbar machen. Genug Pins hast Du. 7. Dein Chip
Kontrollsignale des FDC (A0, CS etc.) an die PMP Addresseingänge legen oder an die Dateneingänge des µC? - Wenn ich den FDC nur im AT/EISA Modus betreibe benötige ich dann überhaupt DMA? - Sollte ich den RST pin vom µC steuern oder an einen Pull-up-Widerstand hängen? Ansonsten würde ich mich über
Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A A2 PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018D Sheet 1 of 2 2006-2016 Microchip
in sehr kurzer Zeit). Bob Supnik schreibt zu dieser Zeit (er hatte damals bei DEC gearbeitet): [c] From 1975, with the introduction of the KL10, until 1991, when NVAX was released, the highest performance processors at DEC were built with ECL (emitter coupled logic) technology. Fast, hot, and not
Der ZX Spectrum hat eine ULA5C, später 6C. Die 5C hat schonmal doppelt so viele Zellen wie die ULA2C des ZX81. Die drei Ziffern am Ende bezeichnen die Metallmaske, also das Programm der ULA.
space +000004B3: 91300119 LDS R19,0x0119 Load direct from data space +000004B5: 0F28 ADD R18,R24 Add without carry +000004B6: 1F39 ADC R19,R25 Add with carry +000004B7: C001 RJMP PC+0x0002 Relative jump 296: iAdress
Rolf W. schrieb im Beitrag #1789384: > W20X4A, Hardware-Version 8C7.C9 Hallo Rolf, Anbei mein backup (W2024A HW 8C7.C9 SW 1.4) hoffe dass das hilft. Martin
loss is marginal and I think compared with some other flaws in the Wittig design it doesn't matter at all. Yesterday evening I watched the temperature drift of my 2024 scope. The cope had room temperature (abt. 18°C) and I activated only channel 1, 5V scale and moved the GND indicator to the 15V
avrdude gibt mir in der txt Datei folgendes aus: avrdude: Version 5.10, compiled on Jan 19 2010 at 10:45:23 Copyright (c) 2000-2005 Brian Dean, http://www.bdmicro.com/ Copyright (c) 2007-2009 Joerg Wunsch System wide configuration file is "C:\WinAVR-20100110\bin\avrdude.conf
wie folgt aus: avrdude -c stk500v2 -p m32 -P com4 -vvvv > "C:\FehlerM32.txt" 2>&1 In der txt Datei steht danach [code] avrdude: Version 5.10, compiled on Jan 19 2010 at 10:45:23 Copyright (c) 2000-2005 Brian
Beispielcode durchlesen: im Linux-sourcecode bietet sich da natürlich die Datei "sound/pci/intel8x0.c" an, dort vielleicht die Funktion [c] static int snd_intel8x0_ich_chip_init(struct intel8x0 *chip, int probing) [/c] als Einstiegspunkt. Wenn du dann die Initialisierung soweit nachprogrammiert
RV370) 5B64 (PCIE), ATI FireMV 2200 PCIE (RV370) 5B65 (PCIE), ATI Radeon Mobility 9200 (M9+) 5C61 (AGP), ATI Radeon Mobility 9200 (M9+) 5C63 (AGP), ATI Mobility Radeon X800 XT (M28) (PCIE), ATI Mobility FireGL V5100 (M28) (PCIE), ATI Mobility Radeon X800 (M28) (PCIE), ATI Radeon X850
MHz [ 14.034] (II) RADEON(0): EDID (in hex): [ 14.034] (II) RADEON(0): 00ffffffffffff00410c46c001010101 [ 14.034] (II) RADEON(0): 0013010368331d782aca45a4564b9c25 [ 14.034] (II) RADEON(0): 125054254a0081809500b300d1c00101 [ 14.034] (II) RADEON(0): 010101010101023a801871382d40582c
für das nicht mehr erhältliche EB1 LiveDesign Board gelten folgende Punkte: Xilinx XC3S1000-4FG456C, wahlweise aber auch mit Altera EP1C12F324C8 Peripherie: LEDs, Dip-Schalter, 6-stellige Siebensegmentanzeige, Taster, Stereo-DAC, zwei 256K x 16 RAMs kein on-board Flash RAM für FPGA-Konfiguration, diese
Boards dieses Herstellers unterstützt Lattice HM-ALC-AS3. Modul mit zwei Altera Stratix™ III EP3S50F780-C2N FPGA oder EP3S150F780-C2N 126 single ended interconnections plus 28 LVDS pairs ALTERA USB Blaster® on board temperature controlled fan's(PWM) Terasic. Terasic ist sozusagen der Haus- und Hoflieferant
,r18 or r17,r19 ; Set bit to 1 _sq32_3: lsr r19 ror r18 ; Shift right mask, C --> end loop eor r17,r19 eor r16,r18 ; Shift right only test bit in result rol T2L ; Bit 0 only set if end of loop rol T2H rol T4L rol T4H ; Shift left remaining argument (C used at _sq32_1) sbrs T2L
Specification located at http://www.microchip.com/packaging N NOTE 1 E1 1 2 3 D E A A2 L A1 c e eB b1 b Units INCHES Dimension Limits MIN NOM MAX Number of Pins N 8 Pitch e .100 BSC Top to Seating Plane A – – .210 Molded Package
->TC_RA=0xFFFF; AT91C_BASE_TC0->TC_RB=0xFFFF; AT91C_BASE_TC0->TC_IER=AT91C_TC_CPCS ; // Interrupt on RC AT91C_BASE_TCB->TCB_BCR=1; int dummy=AT91C_BASE_TC0->TC_IMR; AT91C_BASE_TC0->TC_CCR=AT91C_TC_CLKEN | AT91C_TC_SWTRG
define BUTTON_D AT91C_PIO_PA28 define BUTTON_ROT_A AT91C_PIO_PA31 define BUTTON_ROT_B AT91C_PIO_PA30 define BUTTON_ROT_C AT91C_PIO_PA29 define IR_IN AT91C_PIO_PA5 Wie es weiter geht. Als Betriebsystem habe ich mich für
High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. When B = "Low", blink is off. Alternating display Every 64 frames Cursor z Cursor or Display Shift RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 S/C R/L X X ¾ S/C: Screen/Cursor
High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. When B = "Low", blink is off. Alternating display Every 64 frames Cursor z Cursor or Display Shift RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 S/C R/L X X ¾ S/C: Screen/Cursor
High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. When B = "Low", blink is off. Alternating display Every 64 frames Cursor z Cursor or Display Shift RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 S/C R/L X X ¾ S/C: Screen/Cursor
High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. When B = "Low", blink is off. Alternating display Every 64 frames Cursor z Cursor or Display Shift RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 S/C R/L X X ¾ S/C: Screen/Cursor
High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. When B = "Low", blink is off. Alternating display Every 64 frames Cursor z Cursor or Display Shift RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 S/C R/L X X ¾ S/C: Screen/Cursor
High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. When B = "Low", blink is off. Alternating display Every 64 frames Cursor z Cursor or Display Shift RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 S/C R/L X X ¾ S/C: Screen/Cursor
High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. When B = "Low", blink is off. Alternating display Every 64 frames Cursor z Cursor or Display Shift RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 S/C R/L X X ¾ S/C: Screen/Cursor
High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. When B = "Low", blink is off. Alternating display Every 64 frames Cursor z Cursor or Display Shift RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 S/C R/L X X ¾ S/C: Screen/Cursor
High", cursor blink is on, that performs alternate between all the high data and display character at the cursor position. When B = "Low", blink is off. Alternating display Every 64 frames Cursor z Cursor or Display Shift RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 1 S/C R/L X X ¾ S/C: Screen/Cursor
C++ ein Scherz? http://magazin.c-plusplus.de/artikel/%28Humor%29%20Die%20Entstehungsgeschichte%20von%20C
Timbo1 schrieb im Beitrag #3299968: > C++ ein Scherz? > http://magazin.c-plusplus.de/artikel/%28Humor%29%20Die%20Entstehungsgeschichte%20von%20C Spass am Rande: Es gibt eine Sprache, die sieht im realen Leben wirklich so aus, wie der Jux
details. Input Capture The AVR has an input pin to trigger the input capture event. A signal change at this pin causes the timer value to be read and saved in the Input Capture Register (ICRx). At the same time the Input Capture Flag (ICFx) in the TIFR will be set. This is useful to mea- sure the width
