-
PDF
pm2521ocr.pdf
DOWN | (z) 7 ~Tes SK3 ! s 3 4 LOBATT 10n | i ° +I ASK | 2 ue ' | . : | ” SK4 | a DI919 | be HEF4051 sta388 : 811130 | ‘ Fig.36. Switch decoding | . , | | : , | 51 v153 52 . BAW62 : -R Y C153 ontrol outputs 52 ia Control of the reed relays used for range changing, function switching, ete. isachieved by
in „Pjilips PM2519“ · Markt ·
-
PDF
x31ba001.f10.3__S1D13706_Spec_Rev_10.3_.pdf
powered down and the status of the memory controller is indicated by the Memory Controller Power Save Sta- tus bit (REG[A0h] bit 3). However, memory writes are possible during power save mode because the S1D13706 dynamically enables the memory controller for display buffer writes. 2 GPIO Pins are configured
in „TFT-Display Controller an STM32 über FSMC“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
MS-17631_2.0.pdf
HP_L_ADC R366 R369 G P=2.3x2.3 / 4ohm=1.32W 4.7KR0402 4.7KR0402 6 2 APA2051QBI-TRG_TQFN28 ▯ S C53 C0.015u16X0402 AGND AGND ▯ AGND Bass Speaker Woofer SPEC=3.8ohm / normal 3W,Max 4w C R26 = 30K 27K RMS=3.04V R75 30KR0402 P=3.38x3.38 / 3,8ohm=3W AGND Cost Down F 24.9K RMS=2.81V R343 X_39KR0402 C352 X_C0.033u1600402
in „In Circuit Programmierer für 8-pin 150mil SOIC PM25LD512“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
252039.pdf
S Int Frac 04C Gs (013) 0 0 0 0 0 0 0 0 Int Frac 050 dGdx (014) S S S S S S S S Int Frac 054 dGdy (015) S S S S S S S S Int Frac 058 Bs (016) 0 0 0 0 0 0 0 0 Int Frac 05C dBdx (017) S S S S S S S S Int Frac 060 dBdy (018) S S S S S S S S Int Frac MB86277 MINT Graphics Controller 119 Specifications Rev
in „LCD Display / Controller eines Schweißgerätes prüfen“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
ATtiny26.pdf
the CPU wakes up from Power-down, the selected clock source is used to time the start-up, ensuring sta- ble oscillator operation before instruction execution starts. When the CPU starts from Reset, there is as an additional delay allowing the power to reach a stable level before commencing normal operation
in „ATtiny26(L) Analog-Digital-Wandler ( ADC ) Datenblattübersetzung“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
R32C-152_Users_Manual.pdf
0150h to 0153h) 84 CAN2 receive FIFO +340 to +343 (0154h to 0157h) 85 Reserved +344 to +347 (0158h to 015Bh) 86 Reserved +348 to +351 (015Ch to 015Fh) 87 E dataFlash +352 to +355 (0160h to 0163h) 88 28. “E2PROM Emulation Data Flash” Reserved +356 to +359 (0164h to 0167h) 89 Reserved +360 to +363 (0168h
in „Keine UART Programmierung bei R32C möglich“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
attiny84.pdf
Registers 0x0000 - 0x001F 64 I/O Registers 0x0020 - 0x005F 0x0060 Internal SRAM (128/256/512 x 8) 0x0DF/0x015F/0x025F 5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk cycles as illustrated
in „Attiny 84 ISP?!“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
AVR_ATtiny_24_44_84.pdf
Registers 0x0000 - 0x001F 64 I/O Registers 0x0020 - 0x005F 0x0060 Internal SRAM (128/256/512 x 8) 0x0DF/0x015F/0x025F 5.2.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk cycles as illustrated
in „AVR Programm brennen ohne Bootloader“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
Lang_CDDA.pdf
der 3 Mons, 1.1Interview 25. Nov. 1993,5A 105 4 van Tilburg, J.J.G.Ch. Interview 2. Dez. 1993,6A 008-015 I Ottens, L.F. Interview 12. Okt. 1993,2A 215 vgl. auch GuterlF."Cornpact Disc".IEEE Spectrum, 25(11), 1988, hier: 2Mons, J.J. Interview 25. Nov. 1993,5A 060 S.I04 3ebenda, 5A 082 S van Tilburg, I.I.G.Ch
in „Sample Frequenz 48 KHz vs. 44 KHz“ · Digitale Signalverarbeitung / DSP / Machine Learning ·
-
PDF
PIC16F18344.pdf
0000 r 014h PIR4 CWG2IF CWG1IF TMR5GIF TMR5IF CCP4IF CCP3IF CCP2IF CCP1IF 0000 0000 0000 0000 C y 015h TMR0L TMR0L<7:0> xxxx xxxx xxxx xxxx 1 016h TMR0H TMR0H<7:0> or TMR0<15:8> 1111 1111 1111 1111 017h T0CON0 T0EN — T0OUT T016BIT T0OUTPS<3:0> 0-00 0000 0-00 0000 6 ( 018h T0CON1 T0CS<2:0> T0ASYNC T0CKPS
in „EEPROM Verständnisproblem beim PIC 16F18344“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
PIC16F1939.pdf
CCP3CON 393h — 014h — 094h — 114h CM2CON1 194h EEDATH 214h SSPSTAT 294h PWM1CON 314h PWM3CON 394h IOCBP 015h TMR0 095h OPTION_REG 115h CMOUT 195h EECON1 215h SSPCON1 295h CCP1AS 315h CCP3AS 395h IOCBN 016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSPCON2 296h PSTR1CON 316h PSTR3CON 396h IOCBF 017h TMR1H
in „MPLAB delay und xtalfreq richtig benutzen“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
AT90PWM2_2B_3_3B__2_.pdf
Complete Handler 0x013 rjmp EXT_INT1 ; IRQ1 Handler 0x014 rjmp SPI_STC ; SPI Transfer Complete Handler 0x015 rjmp USART_RXC ; USART, RX Complete Handler 0x016 rjmp USART_UDRE ; USART, UDR Empty Handler 0x017 rjmp USART_TXC ; USART, TX Complete Handler 0x018 rjmp EXT_INT2 ; IRQ2 Handler 0x019 rjmp WDT ; Watchdog
in „Interrupt bem Flankenwechsel beim AVR“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
at90pwm3.pdf
Complete Handler 0x013 rjmp EXT_INT1 ; IRQ1 Handler 0x014 rjmp SPI_STC ; SPI Transfer Complete Handler 0x015 rjmp USART_RXC ; USART, RX Complete Handler 0x016 rjmp USART_UDRE ; USART, UDR Empty Handler 0x017 rjmp USART_TXC ; USART, TX Complete Handler 0x018 rjmp EXT_INT2 ; IRQ2 Handler 0x019 rjmp WDT ; Watchdog
in „Schrittmotorsteuerung mir 90atPWM3“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
DM00031020.pdf
register (SDIO_DCOUNT) . . . . . . . . . . . . . . . . . . 894 28.9.11 SDIO status register (SDIO_STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895 28.9.12 SDIO interrupt clear register (SDIO_ICR) . . . . . . . . . . . . . . . . . . . . . . 896 28.9.13 SDIO mask register (SDIO_MASK) .
in „fsmc am stm32f4“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
r_manuel.pdf
register (SDIO_DCOUNT) . . . . . . . . . . . . . . . . . . 894 28.9.11 SDIO status register (SDIO_STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 895 28.9.12 SDIO interrupt clear register (SDIO_ICR) . . . . . . . . . . . . . . . . . . . . . . 896 28.9.13 SDIO mask register (SDIO_MASK) .
in „Hilfe bei Programmierung STM32F407VG bei TIM1“ · Mikrocontroller und Digitale Elektronik ·
-
PDF
1_AMD_BKDG_Family__15h_Mod_00h-0Fh_BKDG.pdf
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 01 0100 0001 0101 01B8 015C 012E 01C6 0163 01FD 0189 019D B801 5C01 2E01 C601 6301 FD01 8901 9D01 02 0200 0002 0202 0201 02B8 025C 02FD 02C6 028B 0263 024B 0102 B802 5C02 FD02 C602 8B02 6302 4B02 03 0300 0003 0303 03B9 03E4 0372
-
PDF
DM00135183.pdf
register (SDIO_DCOUNT) . . . . . . . . . . . . . . . . . . 1029 29.8.11 SDIO status register (SDIO_STA) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1029 29.8.12 SDIO interrupt clear register (SDIO_ICR) . . . . . . . . . . . . . . . . . . . . . 1030 29.8.13 SDIO mask register (SDIO_MASK) . .
in „STM32F446 FMP I2C kein Open Drain möglich?!“ · Mikrocontroller und Digitale Elektronik ·