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PCF8583P.pdf
locations 1, 2, and 3. Thus, up to 1 million events may be recorded. control/status register = XX0X X1XX. The timer counts up from 0 (or a programmed value) to 99. On overflow, the An event counter alarm occurs when the event counter timer resets to 0. The timer flag (LSB of control/status registers
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PDF
82C250.pdf
LOW dominant 0 4.5 to 5.5 V 1 (or floating) floating floating recessive 1 (1) (1) <2 V (not powered) X floating floating recessive X 2 V < V CC < 4.5 V >0.75V CC floating floating recessive X(1) 2 V < V CC < 4.5 V X(1) floating if floating if recessive X(1) VRs > 0.75V CC VRs > 0.75V CC Note 1. X = donÕt care
in „I2C vs CAN vs Ethernet“ · Mikrocontroller und Digitale Elektronik ·
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PDF
doc7627.pdf
90,930 57 25,084 87 8,576 -2 414,089 28 86,750 58 24,126 88 8,300 -1 390,890 29 82,787 59 23,211 89 8,035 0 369,145 30 79,030 60 22,336 90 7,779 1 348,757 31 75,466 61 21,498 91 7,533 2 329,630 32 72,085 62 20,697 92 7,296 3 311,680 33 68,876 63 19,930 93 7,067 4 294,826 34 65,830 64 19,196 94 6,847 AT90USBKey
in „Problem mit dem TC4469“ · Mikrocontroller und Digitale Elektronik ·
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PDF
TDA5051A.pdf
DATA and TX (see Table 3). IN OUT Table 3 Relationship between DATA and TX IN OUT PD DATA IN TX OUT 1 X (1) high-impedance 0 1 high-impedance (after t ) h 0 0 active with DC offset Note 1. X = donÕt care. handbook, halfpage t W(burst) su th 100% MGK010 Fig.9 Pulse shape characteristics. 1999 May 31 12
in „µC Kommunikation (Signale) über Gleichspannung modulieren“ · Mikrocontroller und Digitale Elektronik ·
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VN5160S-E.pdf
Suggested connections for unused and N.C. pins Connection / PinStatus N.C. Output Input STAT_DIS Floating X X X X X Through 10KΩ Through 10KΩ To ground N.R.(1) X N.R. resistor resistor (1) Not recommended. 6/31 VN5160S-E Electrical specifications 2 Electrical specifications Figure 3. Current and voltage conventions
in „2 Spannungen mit Mosfets schalten“ · Mikrocontroller und Digitale Elektronik ·
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PDF
BM-ATOM1.0-V1.6.pdf
Select IAP function before the programming is started. RGS1 RGS0 IAP Region IAP Related SFR 0 0 EEP0 (0x1C0 ~ 0x1FF) 9 DPH / DPL : Least significant 6-bit address for IAP. 0 1 EEP1 (0x3C0 ~ 0x3FF) 1 0 INFO (0x0 ~ 0x7) 9 GDH / GDL : 8-bit data buffer for read or write by IAP. 1 1 Reserved 9 IAPCON : IAP
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WM8978.pdf
PACKAGE MOISTURE PEAK SOLDERING RANGE SENSITIVITY LEVEL TEMPERATURE o WM8978GEFL/V -25°C to +85°C 32-lead QFN (5 x 5 mm) MSL3 260 C (Pb-free) o WM8978GEFL/RV -25°C to +85°C 32-lead QFN (5 x 5 mm) MSL3 260 C (Pb-free, tape and reel) Note: Reel quantity = 3,500 PTD Rev 2.6 November 2005 w 4 Preliminary
in „GSM + GPS Modul von Pollin“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Preisliste_2008-09_Stand_Aug08.pdf
2 Stück 32,00 615575 EasyPhor PAGE Mini U-förmiges Glas, Spacer 2 mm 2 Stück 32,00 615576 EasyPhor PAGE Mini Begrenzer-Platte,10x10 cm 1 Stück 10,00 615577 EasyPhor PAGE Mini Spacer - 10 cm,0.5 mm 2 Stück 11,00
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P14067EJ2V0DS00.pdf
23.33 12.95 –29.75 0.42 0.038 26.985 9.00 1.39 3500.0000 21.99 12.85 –28.44 0.47 0.038 26.594 7.83 1.32 4000.0000 20.87 12.70 –27.53 0.54 0.035 24.253 6.92 1.25 4500.0000 19.95 12.53 –26.98 0.60 0.034 23.581 6.21 1.22 5000.0000 19.11 12.38 –26.29 0.67 0.032 22.154 5.53 1.21 5500.0000 18.50 12.29 –26.00
in „Vorverstärker für magnetische Loop“ · HF, Funk und Felder ·
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PDF
00643b.pdf
PIC16C7X Data Sheet. Decode 162 10 PWM duty cycle = DC<10:0> Tosc (TMR2 prescale value) PIC17CXXX Encode 203 13 97 x Decode 164 10 where DC<10:0> = 2 where x = bits of resolution 1 / 32 kHz = 2x (1 / 20 MHz)
in „Messdaten Kompression“ · Digitale Signalverarbeitung / DSP / Machine Learning ·
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PDF
GCC_Tut_Test.pdf
} 32 // Funktion aufrufen , wenn Bit 0 und Bit 2 gesetzt sind 33 if ( ( PINA & 0x05 ) == 0x05 ) { // nur wahr , wenn beide Bits gesetzt 34 test1(); 35 } 36 // Funktion test2() aufrufen , wenn Bit 0 gel
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M95160_EEPROM.pdf
tCLHL tHHCH C tCLHH tHLQZ tHHQV Q D HOLD AI01448B 31/40 M95160, M95080 Figure 17. Output Timing S tCH C tCLQV tCLQV tCL tSHQZ tCLQX tCLQX Q LSB OUT tQLQH tQHQL ADDR.LSB IN D AI01449D 32/40 M95160, M95080 PACKAGE MECHANICAL Figure 18. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline E b2
in „SPI EEPROM M95160: read/write probleme, erhalte immer FFh!“ · Mikrocontroller und Digitale Elektronik ·
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PDF
JBT6K71-AS_A__v1.42_2006-02-07_E.PDF
OUT41 -4576 823 480 OUT1 -6336 823 12 Rev.1.42/2006-02-07 JBT6K71-AS(A) Pad Coordinates (5) [Unit: μm] X- Y- X- Y- X- Y- No. Pin Name Coordinate Coordinate No. Pin Name Coordinate Coordinate No. Pin Name Coordinate Coordinate 481 DMY30 -6380 930 482 DMY31 -6424 823 483 DMY32 -6468 930 484 DMY33 -6512 823
in „LCD aus Benq EL71 Handy“ · Mikrocontroller und Digitale Elektronik ·
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PDF
enc28j60.pdf
0159h tsv[23:16] Status Vector Status Vector 016Ah tsv[31:24] Written by the Hardware 016Bh tsv[39:32] 016Ch tsv[47:40] 016Dh tsv[51:48] 016Eh Start of the Next Packet To achieve the example layout shown in Figure 7-2 and DMA and transmission engine share the same memory to transmit a packet, the host
in „ENC28J60 Resetpin“ · Mikrocontroller und Digitale Elektronik ·
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MCP320412-bitA-DConverterDatasheet.pdf
brought high and back low to initiate communication. The first clock received with CS low INhigh will 1 X 0 0 single-ended CH0 constitute a start bit. The SGL/DIFF bit follows the start 1 X 0 1 single-ended CH1 bit and will determine if the conversion will be done 1 X 1 0 single-ended CH2 using single-ended
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IA4421-DS.pdf
Configuration Setting Command Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POR 1 0 0 0 0 0 0 0 el ef b1 b0 x3 x2 x1 x0 8008h Bit el enables the internal data register. Bit ef enables the FIFO mode. If ef = 0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output. x3 x2 x1 x0 Crystal Load
in „Software SPI zur Chip Konfig“ · Mikrocontroller und Digitale Elektronik ·
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PDF
1407fa.pdf
Data Acquisition Systems + – + ■ Uninterrupted Power Supplies tially. The absolute voltage swing for CH0 , CH0 , CH1 – ■ Multiphase Motor Control and CH1 extends fromground to the supply voltage. ■ I & Q Demodulation Theserialinterfacesendsoutthetwoconversionresultsin ■ Industrial Control 32clocks forcompatibilitywithstandardserialinterfaces
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CS4272.pdf
48 Fs 128 32, 64 Fs DS593PP3 27 CS4272 5.1.4 16-Bit Auto-Dither The CS4272 will auto-configure to output properly dithered 16-bit data when placed in Slave Mode and a 32x SCLK to LRCK ratio is used. In this configuration
in „was ist "ATAPI channel mixing" Warum kein Ausgangssignal?“ · Mikrocontroller und Digitale Elektronik ·
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PDF
LTC1407CMSE.pdf
Data Acquisition Systems + – + Uninterrupted Power Supplies tially. The absolute voltage swing for CH0 , CH0 , CH1 – Multiphase Motor Control and CH1 extends fromground to the supply voltage. I & Q Demodulation Theserialinterfacesendsoutthetwoconversionresultsin Industrial Control 32clocks forcompatibilitywithstandardserialinterfaces
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Tiny15L.pdf
Microcontroller Advanced RISC Architecture – 90 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation Nonvolatile Program and Data Memories – 1K Byte In-System Programmable Flash Program Memory Endurance: 1,000 Write/Erase Cycles – 64 Bytes
in „Frequenzschalter“ · Mikrocontroller und Digitale Elektronik ·
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PDF
TDA5051A_-_PowerLine.pdf
DATA and TX (see Table 3). IN OUT Table 3 Relationship between DATA and TX IN OUT PD DATA IN TX OUT 1 X (1) high-impedance 0 1 high-impedance (after t ) h 0 0 active with DC offset Note 1. X = donÕt care. handbook, halfpage t W(burst) su th 100% MGK010 Fig.9 Pulse shape characteristics. 1999 May 31 12
in „Probleme mit PLC-Modem-Chip TDA5051“ · Haus & Smart Home ·
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PDF
BPW_34.pdf
0.8(0.031) ) ) ) 0.6(0.024) 0...5˚ 7 5 0 0 8 4 1 1 5.08(0.200) Photosensitivearea spacing 2.65(0.104)x2.65(0.104) GEOY6643 BPW 34 S ) ) ) Chipposition 4 4 1 . 0. 4 . 1.1(0.043) ( 0( 0 ( . 1. 0 0 . 0.9(0.035) 1 1 . 0 0 0 ( ) ) 5˚ 0 0 6.7(0.264) . . . 0 ( ( 6.2(0.244) 0 0 4.5(0.177) 4.3(0.169) 1.8(0.071
in „Photodiode messen“ · Analoge Elektronik und Schaltungstechnik ·
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PDF
10350.pdf
STR71xF ARM7TDMI™ 32-bit MCU with Flash, USB, CAN 5 timers, ADC, 10 communications interfaces Features ■ Core – ARM7TDMI 32-bit RISC CPU LQFP64 – 59 MIPS @ 66 MHz from SRAM 10 x 10 LQFP144 – 45 MIPS @ 50 MHz
in „ARM7TDMI 32-bit RISC CPU - STR 712 FR2 T6 zu verkaufen“ · Markt ·
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Datei
DC_3840EEprom_cut.lst
F5 08 mov 08h, a 034F 12 03 94 lcall 0394h 0352 F5 4A mov 4Ah, a 0354 12 03 94 lcall 0394h 0357 F5 32 mov 32h, a 0359 12 13 73 lcall 1373h 035C 20 06 2D jb 20h.6, 038Ch 035F 90 15 75 mov dptr, #1575h 0362 12 03 94 lcall 0394h 0365 52 30 anl 30h, a 0367 12 03 94 lcall 0394h 036A B5 30 1F cjne a, 30h, 038Ch 036D 12 03 94 lcall 0394h 0370 F5 32 mov 32h, a 0372 12 13 73 lcall 1373h 0375 20 06 14 jb 20h.6, 038Ch 0378 90 15 75 mov dptr, #1575h 037B 12 03 94 lcall 0394h 037E 52 30 anl 30h, a 0380 12 03 94 lcall
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Was hört ihr für Musik ?
: Ja, Blue war ein schönes Album mit einigen Preziosen. Hier ist ein Cover: https://youtu.be/tq32P9xIv9E
watch?v=rvYuoWyk8iU&list=PLRAJSUF2MG_wI0MmTPPZOzcuEI85OKXfT&index=13 https://www.youtube.com/watch?v=x-5zEb1oS9A&list=PLRAJSUF2MG_wI0MmTPPZOzcuEI85OKXfT&index=32
Offtopic ·TheMason · ·2854 Antworten
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slau049f.pdf
Hardware Multiplier Block Diagram 15 rw 0 MPY 130h MPYS 132h 15 rw 0 OP1 OP2 138h MAC 134h MACS 136h 16 x 16 Multipiler Accessible Register MPY = 0000 MACS MPYS 32−bit Adder MAC MPY, MPYS MAC, MACS Multiplexer 32−bit Multiplexer SUMEXT 13Eh C S RESHI 13Ch RESLO 13Ah 15 r 0 31 rw rw 0 7-2 Hardware Multiplier
in „Umrechnung: C-Code->Assembler-Code->Cycles“ · Mikrocontroller und Digitale Elektronik ·
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PDF
Vishay_Diode_Marking.pdf
Semiconductor Logo Part Number V20100S VF20100S VB20100S VI20100S 0621X 0621X 0621X 0621X Date Code NC A Circuit Diagram 06 21 X TO-220AB ITO-220AB TO-263AB TO-262AA Factory Designator Week 21st Year 2006 Logo MBR1060 MBRF1060 MBRB1060 Part Number 0621X 0621X 0621X Date
in „Unbekanntes Bauteil“ · Mikrocontroller und Digitale Elektronik ·
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PDF
trc101.pdf
configurable. The receive packet structure when using the synchronous pattern should be: PREAMBLE 0xAA PREAMBLE 0xAASYNCH BYTE 0x2DSYNCH BYTE 0XD4DATA [N] DATA [N+1]DATA [N+2 Any packet sent, whether using the synchronous pattern or not, should always start with a preamble sequence of alternating 1’s and 0’s, such as 1-0-1-0-1. This corresponds to sending a 0xAA or 0x55. The preamble may be one byte (Fast CR lock) or two bytes (Slow CR lock). The next two bytes should be nd the synchronous pattern. In this case, data storage begins immediately following the
in „bidirektionale RS232 Funkbrücke mit RFM12“ · Projekte & Code ·
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PDF
M95256_EEProm_Farnell_69998.pdf
EEPROM) devices are accessed by a high speed SPI-compatible bus. The memory array is organized as 32768 x 8 bit (M95256) and 16384 x M95xxx 8 bit (M95128). The device is accessed by a simple serial interface S 1 8 VCC that is SPI-compatible. The bus signals are C, D Q 2 7 HOLD and Q, as shown in Table 2.
in „SPI EEProm Hilfe gesucht“ · Mikrocontroller und Digitale Elektronik ·
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PDF
CS4272_F1.pdf
48 Fs 128 32, 64 Fs DS593F1 25 CS4272 5.1.4 16-Bit Auto-Dither The CS4272 will auto-configure to output properly dithered 16-bit data when placed in Slave Mode and a 32x SCLK to LRCK ratio is used. In this configuration
in „darf der Chip so warm werden?“ · Mikrocontroller und Digitale Elektronik ·
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PDF
GH79L4N_FEB2002_.pdf
Smoother tracking Less responsive (large inertia) but smoother tracking record record “Xn”: Dynamic Index X1-X3 [2] (n/a) {X2) Index Characteristics Remarks 1 More accurate Higher accuracy but less frequent positioning positioning 2 Averaged Averaged tuning (initial setting) 3 More frequent More frequent positioning
in „GPS Receiver Furuno / Tecsys GH-79“ · Mikrocontroller und Digitale Elektronik ·
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Datei
FONT6x8.txt
;6x8 FONT db 000h,000h,000h,000h,000h,000h; 0x00 db 000h,03Eh,045h,051h,045h,03Eh; 0x01 db 000h,03Eh,06Bh,06Fh,06Bh,03Eh; 0x02 db 000h,01Ch,03Eh,07Ch,03Eh,01Ch; 0x03 db 000h,018h,03Ch,07Eh,03Ch,018h; 0x04
in „SED1520 - EA DIP122-5“ · Mikrocontroller und Digitale Elektronik ·
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PDF
slau056e.pdf
SCFI1 are cleared. Time must be allowed for the DCO to settle on the proper tap for normal operation. 32 ACLK cycles are required between taps requiring a worst case of 28 x 32 ACLK cycles for the DCO to settle. FLL+ Clock Module 4-7 FLL+ Clock Module Operation 4.2.6 DCO Modulator The modulator mixes two
in „MSP430FG439 mit LCD“ · Mikrocontroller und Digitale Elektronik ·
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PDF
slau056e.pdf
SCFI1 are cleared. Time must be allowed for the DCO to settle on the proper tap for normal operation. 32 ACLK cycles are required between taps requiring a worst case of 28 x 32 ACLK cycles for the DCO to settle. FLL+ Clock Module 4-7 FLL+ Clock Module Operation 4.2.6 DCO Modulator The modulator mixes two
in „MSP430 LCD Controller“ · Mikrocontroller und Digitale Elektronik ·
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PDF
PCA82C250_PHI.pdf
LOW dominant 0 4.5 to 5.5 V 1 (or floating) floating floating recessive 1 (1) (1) <2 V (not powered) X floating floating recessive X 2 V < V CC < 4.5 V >0.75V CC floating floating recessive X(1) 2 V < V CC < 4.5 V X(1) floating if floating if recessive X(1) VRs > 0.75V CC VRs > 0.75V CC Note 1. X = donÕt care
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PDF
tda8444.pdf
in Table 1. 2 Table 1 IC-bus format (see note 1) S 0 1 0 0 A2 A1 A0 0 A I3 I2 I1 I0 SD SC SB SA A X X D5 D4 D3 D2 D1 D0 A P Note 1. S = START condition; A2 to A0 = programmable address bits; A = Acknowledge; I3 to I0 = Instruction bits; SD to SA = subaddress bits; X = donÕt care; D5 to D0 = data bits; P = STOP condition. Valid addresses are: TDA8444 and TDA8444AT: 40H, 42H, 44H, 46H, 48H, 4AH, 4CH and 4EH TDA8444T: 48H, 4AH, 4CH and 4EH (A2 is always logic 1). All other addresses cannot be acknowledged by the circuit. The actual slave address depends on the programmable 2 address bits A2, A1 and
in „Verzweifle an TWI Code Mega8-TDA 8444“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ADS8364.pdf
6x CH B1+ CDAC 16 CH B1– S/H Comp Amp Data Input/Output CH C0+ CDAC CH C0– Amp Comp SAR HOLDC CH C1+ CDAC CH C1– S/H Amp Comp REFIN REFOUT 2.5Vrnal Reference Please be aware that an important notice concerning
in „ADC ADS8364 ansprechen“ · Mikrocontroller und Digitale Elektronik ·
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PDF
FARNELL_STM25P40.pdf
S tHLCH tCHHL tHHCH C tCHHH tHLQZ tHHQX Q D HOLD AI02032 29/34 M25P40 Figure 24. Output Timing S tCH C tCLQV tCLQV tCL tSHQZ tCLQX tCLQX Q LSB OUT tQLQH tQHQL ADDR.LSB IN D AI01449D 30/34 M25P40 PACKAGE MECHANICAL SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width h x 45˚ A C B CP e D N
in „SPI Flash Speicher beschreiben“ · Mikrocontroller und Digitale Elektronik ·
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PDF
M95512.pdf
EEPROM) devices are accessed by a high speed SPI-compatible bus. The memory array is organized as 65536 x 8 bit. The device is accessed by a simple serial interface M95xxx that is SPI-compatible. The bus signals are C, D and Q, as shown in Table 2. and Figure 2. The device is selected when Chip Select (S
in „M95640-EEPROM per SPI an ATmega 8 antwortet nicht“ · Mikrocontroller und Digitale Elektronik ·
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PDF
cfspc3_0.pdf
0: identifier 0=compare User password 1=compare Master password Bit 1-15: Reserved 1-16 Password (32 bytes) 17-256 Reserved 6.2.1.23 Security Erase Prepare - F3h Bit -> 7 6 5 4 3 2 1 0 Command (7) F3h C/D/H (6) 1 LBA 1 Drive X Cyl High (5) X Cyl Low (4) X Sec Num (3) X Sec Cnt (2) X Feature (1) X Figure
in „Lucky-page@gmx.de“ · Mikrocontroller und Digitale Elektronik ·
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PDF
msp430f413.pdf
LPM0) VCC = 2.2 V 32 45 (MCLK)= f(SMCLK)= 0.5 MHz, I(LPM0) f = 32,768 Hz, XTS_FLL = 0 TA= −40 C to 85 C µA (ACLK) VCC = 3 V 55 70 FN_8=FN_4=FN_3=FN_2=0 C41x Low-power mode, (LPM0) F41x VCC = 2.2 V 57 70 (MCLK)= f(SMCLK)=
in „MSP430F413 Analog eingänge“ · Mikrocontroller und Digitale Elektronik ·
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PDF
ST24C32_ST24C64_STM.pdf
tCHDX STOP WRITE CYCLE START CONDITION CONDITION AI00795B 12/18 M24C64, M24C32 Table 11. Ordering Information Scheme Example: M24C64 – R MN 1 T Memory Capacity Option 64 64 Kbit (8K x 8) T Tape and Reel Packing 32 32 Kbit (4K x 8) Operating Voltage blank 4.5 V to 5.5 V W 2.5 V
in „I²c mit Bascom und ATmega“ · Mikrocontroller und Digitale Elektronik ·
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PDF
PCF8583.pdf
locations 1, 2, and 3. Thus, up to 1 million events may be recorded. control/status register = XX0X X1XX. The timer counts up from 0 (or a programmed value) to 99. On overflow, the An event counter alarm occurs when the event counter timer resets to 0. The timer flag (LSB of control/status registers
in „RTC PCF8583 einen Interrupt ausloesen“ · Mikrocontroller und Digitale Elektronik ·
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PDF
CompactFlashSpecifications.pdf
4.25mm (.167 in.) all other pins power 5.00mm (.197 in.) 1, 13, 38, 50 43.03mm ± 0.08 (1.694 in.) 2X 0.89mm ± 0.05 (.035 in.) 2X 6.73mm ± 0.08 (.265 in.) A 4.19mm ± 0.08 (.165 in.) 11.18mm ± 0.05 A (.440 in.) 6.73mm ± 0.08 (.265 in.) 2X 3.00mm ± 0.05 2.92mm —A— (.118 in.) (.115 in.) 12.70mm 1.02mm (
in „CompactFlash im I/O Mode“ · Mikrocontroller und Digitale Elektronik ·
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PDF
slas272d.pdf
select P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 input P2IN 028h POST OFFICE BOX 655•DALLAS, TEXAS 75265 17 MSP430x13x, MSP430x14x MIXED SIGNAL MICROCONTROLLER
in „MSP430 Interrupt Port1“ · Mikrocontroller und Digitale Elektronik ·
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PDF
MAX534.pdf
1 1 0 0 X X X X X X X X X Software shutdown (provided PDE is high) 0 0 1 0 X X X X X X X X X UPO goes low. 0 1 1 0 X X X X X X X X X UPO goes high. 0 0 0 0 X X X X X X X X X No operation (NOP); shift data in shift registers. Set DOUT phase—SCLK rising (mode 1). DOUT 1 1 1 0 X X X X X X X X X clocked out on rising edge of SCLK. All DACs updated from their respective input registers. Set DOUT phase—SCLK falling (mode 0). DOUT 1 0 1 0 X X X X X X X X X clocked out on falling
in „D/A Wandler und der reference pin...“ · Mikrocontroller und Digitale Elektronik ·
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PDF
PCF8591.pdf
A A 1 A2 b b c D(1) E(1) e e L M M w Z(1) max. min. max. 1 1 E H max. mm 4.7 0.51 3.7 1.40 0.53 0.32 21.8 6.48 2.54 7.62 3.9 8.25 9.5 0.254 2.2 1.14 0.38 0.23 21.4 6.20 3.4 7.80 8.3 inches 0.19 0.020 0.15 0.055 0.021 0.013 0.86 0.26 0.10 0.30 0.15 0.32 0.37 0.01 0.087 0.045 0.015 0.009 0.84 0.24 0.13
in „Datentransfer an PCF8591“ · Mikrocontroller und Digitale Elektronik ·
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PDF
93LC66.pdf
) 11 EWDS 1 00 0 0 X X X X X X — HIGH-Z 11 EWEN 1 00 1 1 X X X X X X — HIGH-Z 11 READ 1 10 A7 A6 A5 A4 A3 A2 A1 A0 — D15 – D0 27 WRITE 1 01 A7 A6 A5 A4 A3 A2 A1 A0 D15 – D0 (RDY/BSY) 27 WRAL 1 00 0 1 X X X X X X D15 – D0
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PDF
SW016_125kHz_reader_DSv2.5.PDF
60K 0.25W 1% 21 1 R13 3.3K 0.25W 1% 22 2 SW1, SW2 switch RM5-N48/250, Siemens, Matsushita 23 1 T1 3 x 8 turns Components ø 0.74 coated wire 24 1 U1 SW016 25 1 U2 LM324 § APPLICATION SCHEMATICS L1 1 2 345uH 12V Dimension=500x500mm/13turns/1.7mm D1 D2 D3 C1 8 T1 4 10n Q1 BA159 6 4.7n 2M BA159 BA159 BA159
in „Kontaklose Chipkarten????“ · Mikrocontroller und Digitale Elektronik ·
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PDF
SJA1000_3.pdf
bit X. Table 32 TX identifier 4 (EFF); CAN address 20; note 1 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ID.4 ID.3 ID.2 ID.1 ID.0 X(2) X (3) X (3) Notes 1. ID.X means identifier bit X. 2. DonÕt care; recommended
in „Can Controller "SJA1000" Probleme mit Register“ · Mikrocontroller und Digitale Elektronik ·