Z80 6502x Internal Architecture INTERNAL DATABUS 8 BIT MUX MUX TEMP ACU ALU ADR BUS CONTROL BUS ADDRESS BUS DATA BUS CONTROL SECTION INDEX REGISTER STACK POINTER PC INSTRUCTION DECODE CLOCK GENERATOR
; Z80 emulator with CP/M support. The Z80-specific instructions themselves actually aren't ; implemented yet, making this more of an i8080 emulator. ; ; Copyright (C) 2010 Sprite_tm ; ; This program is free
and the syntax of the Z80 assembly language are described in the "Z80 Assembly Language Handbook" published by Zilog and are included at the end of this manual as a reference. The assembler imple- ments certain extensions to
WR,INT,M1,NMI,MREQ,IOREQ,TCLOCK,WAIT,RESET_INV C V V 1 p p s Multi I/O Chip Timer r SIO p 1 k 4 R 2 Z80CPU 27C128 8255 Z80_STI s AS6C1008 p M1 out27 M1 A0 30 out A0 A0 in10 A0 D0/O0 11 hiD00 D0 io 34 D0 PA0 4 ioPA0 A0 in 35 A0 C s MREQ out19 MREQ A1 31 out A1 A0 in12 A0 I/O0 13ioD0 A1 in 9 A1 D1/O1 12
INT,M1,NMI,MREQ,IOREQ,TCLOCK,WAIT,RESET_INV C V 0 V 0 u u p s Multi I/O Chip Timer r SIO p 1 0 R 2 4 Z80CPU M27C64 8255 Z80_STI s M1 out27 30 out A0 AS6C1008 A0 in 10 11hiD00 D0 io34 4 ioPA0 A0 in35 p M1 A0 A0 O0 D0 PA0 A0 C s MREQout19 MREQ A1 31 out A1 A0 in12 A0 I/O0 13 ioD0 A1 in 09 A1 O1 12hiD10
INT,M1,NMI,MREQ,IOREQ,TCLOCK,WAIT,RESET_INV C V 0 V 0 u u p s Multi I/O Chip Timer r SIO p 1 0 R 2 4 Z80CPU M27C64 8255 Z80_STI s M1 out27 30 out A0 AS6C1008 A0 in 10 11hiD00 D0 io34 4 ioPA0 A0 in35 p M1 A0 A0 O0 D0 PA0 A0 C s MREQout19 MREQ A1 31 out A1 A0 in12 A0 I/O0 13 ioD0 A1 in 09 A1 O1 12hiD10
INT,M1,NMI,MREQ,IOREQ,TCLOCK,WAIT,RESET_INV C V 0 V 0 u u p s Multi I/O Chip Timer r SIO p 1 0 R 2 4 Z80CPU M27C64 8255 Z80_STI s M1 out27 30 out A0 AS6C1008 A0 in 10 11hiD00 D0 io34 4 ioPA0 A0 in35 p M1 A0 A0 O0 D0 PA0 A0 C s MREQout19 MREQ A1 31 out A1 A0 in12 A0 I/O0 13 ioD0 A1 in 09 A1 O1 12hiD10
WR,INT,M1,NMI,MREQ,IOREQ,TCLOCK,WAIT,RESET_INV C V V 1 p p s Multi I/O Chip Timer r SIO p 1 k 4 R 2 Z80CPU 27C128 8255 Z80_STI s AS6C1008 p M1 out27 M1 A0 30 out A0 A0 in 10 A0 D0/O0 11hiD00 D0 io34 D0 PA0 4 ioPA0 A0 in35 A0 C s MREQout19 MREQ A1 31 out A1 A0 in12 A0 I/O0 13 ioD0 A1 in 09 A1 D1/O1 12hiD10
WR,INT,M1,NMI,MREQ,IOREQ,TCLOCK,WAIT,RESET_INV C V V 1 p p s Multi I/O Chip Timer r SIO p 1 k 4 R 2 Z80CPU 27C128 8255 Z80_STI s AS6C1008 p M1 out27 M1 A0 30 out A0 A0 in 10 A0 D0/O0 11hiD00 D0 io34 D0 PA0 4 ioPA0 A0 in35 A0 C s MREQout19 MREQ A1 31 out A1 A0 in12 A0 I/O0 13 ioD0 A1 in 09 A1 D1/O1 12hiD10
WR,INT,M1,NMI,MREQ,IOREQ,TCLOCK,WAIT,RESET_INV C V V 1 p p s Multi I/O Chip Timer r SIO p 1 k 4 R 2 Z80CPU 27C128 8255 Z80_STI s AS6C1008 p M1 out27 M1 A0 30 out A0 A0 in 10 A0 D0/O0 11hiD00 D0 io34 D0 PA0 4 ioPA0 A0 in35 A0 C s MREQout19 MREQ A1 31 out A1 A0 in12 A0 I/O0 13 ioD0 A1 in 09 A1 D1/O1 12hiD10
ELEKTRONIKSPIEGEL ZAHLEN,DATEN,FAKTEN AUFGEMERKT g März1976:DerZ80kommtalsAlternativezumIntel8080 . n m DerZ80istein8-Bit-Mikroprozessor,der1976vonZilog wieeineeinzige5-V-Versorgungsspannung,eineein- m alsAlternativezumIntel8080entwickeltwurde.Das gebauteRefresh-SteuerungfürdenArbeitsspeicher
0 1 2 3 4 5 6 7 8 9 A B C D E F 0 nop ld bc, ld (b inc bc inc b dec b ld b,n rlca ex af, add h ld dec bc inc c dec c ld c,n rrca nn c),a af' l,bc a,(bc) 1 djnz d ld de, ld (d inc de inc d dec d ld d,n rla jr d add h ld dec de inc e dec e ld e,n rra nn e),a l,de a,(de) jr nz, ld hl, ld (n add h ld h 2 d nn n),hl inc hl inc h dec h ld h,n daa jr z,d l,hl l,(nn) dec hl inc l dec l ld l,n cpl jr nc, ld sp, ld (n inc (h dec (h ld (h add h ld 3 inc sp scf jr c,d dec sp inc a dec a ld a,n ccf d nn n),a l) l) l),n l,sp a,(nn) 4 ld b,b ld b,c ld b,d ld b,e ld b,h ld b,l ld ld b,a ld c,b ld c,c ld c,d ld
7432N C C A[0..15],CE_RAM,CE_ROM,CE_PIO,RD,WR,INT,M1,MREQ,IOREQ C V V p p s2 s pOe Sp w p 1 4 R e Z80CPU EEPROM2764 8255 U$2 1pi aS out 0 30out A0 ASC6-1008 A0 in 0 11 hiD00 D0 io 04 4 ioPA0 A0 in 0 p out 0 M1 A0 31out 0 in 02 13io 0 in 09 A0 O0 12 hiz 0 io 03 D0 PA0 3 io 0 in 0 A0 C 1 io 0 a MREQ
C A[0..15],CE_RAM,CE_ROM,CE_PIO,RD,WR,INT,M1,MREQ,IOREQ C C C V 0 V 0 su s pdr Sp r p 1 0 R 1 4 ci Z80CPU EEPROM2764 8255 Z80_STI sS M1 out 0 30 out A0 SRAM A0 in 0 11 hD0 0 D0 io 0 4 ioPA0 A0 in 05 p M1 A0 A0 O0 D0 PA0 A0 C s MREQout 0 MREQ A1 31 out A1 A0 in 0 A0 I/O0 13 ioD0 A1 in 9 A1 O1 12 hD1
..15],CE_RAM,CE_ROM,CE_PIO,RD,WR,INT,M1,MREQ,IOREQ C C C V 0 V 0 1u u pdr s ip S 0 w p 1 k 4 R e 2 Z80CPU M27C64 8255 Z80_STI 1pi aS M1 out 07 30 out 0 A0 AS6C1008_128KB_RAM A0 in 00 11 hizD0 D0 io 04 4 io PA0 A0 in 05 p M1 A0 A0 O0 D0 PA0 A0 C s MREQ out 09 MREQ A1 31 out 0 A1 A0 in 02 A0 I/O0 13 ioD0
,INT,M1,NMI,MREQ,IOREQ,TCLOCK C V V 0 0 su s pdr Multi I/O Chip Sp Timer r SIO p 0 1 k 4 ok R dr 2 Z80CPU M27C64 8255 Z80_STI 1Si p M1 out 0 27 M1 A0 30 out 0 A0 AS6C1008 A0 in 010 A0 O0 11 hiz D0 D0 io 034 D0 PA0 4 io 0PA0 A0 in 035 ok A0 0 MREQ out 0 19 31 out 0 A1 A0 in 012 13 io 0D0 A1 in 0 9 12
Matthias Buchhorn buchhorn@fhtw-berlin.de Kurze Übersicht über die Befehle des Z80 Abkürzungen: r,r’ - Einfachregister A, B, C, D, E, H, L dd - Doppelregister BC, DE, HL, SP qq - Doppelregister AF, BC, DE, HL pp - Doppelregister BC, DE, SP n - 8-Bit-Konstante nn - 16-Bit-Konstante
out 0 GND E P VCC S pas 1 2 pasu1p 0 4050N pas 1 4 pas 1 SD Karten Slot PB7 pas 1 6 pas 1 SPI_MOSI p z80_peripherie ISP s 09.12.2014 15:19:30 GND Sheet: 1/1 1 2 3 4 5 6 7 8 10.12.2014 00:26:24 K:\Z80\eagle\z80_peripherie.sch (Sheet: 1/1)
1 ae 7432N C pp A[0..15],CE_RAM,CE_ROM,CE_PIO,RD,WR,INT,M1,MREQ,IOREQ C S V 0u 1 ps R r 0 ic 4 aS Z80CPU IC4 U$2 p out 0 30out 0 IC5 EPROM io 04 4 io 0 in 0 a M1 A0 A0 D0 D0 PA0 PA0 A0 A0 C p out 0 MREQ A1 31out A1 A0 in 02 A0 I/O0 13ioD0 pwr 0 VCC D1 io 03 D1 PA1 3 ioPA1 A1 in 0 A1 STI C TA0 1 io
7432N C s C A[0..15],CE_RAM,CE_ROM,CE_PIO,RD,WR,INT,M1,MREQ,IOREQ C V V 1u p ar s pip S 0 w p 1 4 R dr Z80CPU EEPROM2764 8255 U$2 1Si p out 0 M1 A0 30out A0 ASC6-1008 A0 in 0 A0 O0 11 hiD00 D0 io 04 D0 PA0 4 ioPA0 A0 in 0 A0 0 out 0 31out A1 A0 in 02 13ioD0 A1 in 09 12 hiD10 D1 io 03 3 ioPA1 A1 in 0 STI
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