AVRASM ver. 2.1.42 C:\Dokumente und Einstellungen\inet\Eigene Dateien\sid\main.asm Sun May 03 21:49:28 2015 C:\Dokumente und Einstellungen\inet\Eigene Dateien\sid\main.asm(2): Including file 'C:\Dokumente und Einstellungen\inet\Eigene Dateien\sid\m162def.inc' C:\Dokumente
Bus Voltage (-0.3 V to 28 V) High-Side Shunt Load Low-Side Shunt IN+ IN- TI Device V ADC X Power Register SDA SCL Current Register I2C-, SMBus-, Compatible Interface Voltage Register ALERT A0 Alert Register VS CBYPASS 0.1 µF GND High-Side or Low-Side Sensing Application
9 8 3 3 IC3C + 0 1 0 6 4 4 2 C 1 C 1 C 1 C D +C5 V C1 V C2 V C3 V C4 G IC2P IC1P IC3P IC4P CF-IF (SIDE) für Z180-Stamp 10µ N 100n N 100n N 100n N 100n 1 G 8 G 7 G 7 G TITLE: SIDE D G Document Number: REV: A Date: 27.05.2016 10:47 Sheet: 1/1 27.05.2016 11:01 B:\Privat\AVRCPM\SVN_Mikro\trunk\stamp\SIDE\sheet\SIDE.sch (Sheet: 1/1)
74LV125 9 8 A2 VCC IC3C 1 2 C 1 C 1 C 1 C V V V V N + C5 C1 C2 C3 C4 G IC2P IC1P IC3P IC4P CF-IF (SIDE) für Z180-Stamp 10µ D 100n D 100n D 100n D 100n G G G G 1 8 7 7 TITLE: SIDE1 N G Document Number: REV: A Date: 31.05.2016 15:30 Sheet: 1/1
FET_IRLMS6802DBF T300 UIN S J306 UIN LED1 1 D9 6 3 G 3 n IO-SW ON GND 1 k 3 0 J305 2 5 R 1 C 1 VIN VOUT F +5V 4 F 3 4 5 n LOW -> Ausgeschaltet GND_P 8 0 VIN VOUT C 0 HIGH -> Eingeschaltet GND_P C 1 FPF1005 1 R315 T302 IO-SW GND_P1 GND_P1 4k7 T_BC817_NPN GND_P Datum Name Bearb. <undefined> <DRAWN> <undefined> Gepr. <TITLE> Norm. 1 1 <COMPANY> Zust. Aenderung Datum Name Datei Name: (Ers.fuer:) (Ers.durch:)
FET_IRLMS6802DBF T300 UIN S J306 UIN LED1 1 D9 6 3 G 3 n IO-SW ON GND 1 k 3 0 J305 2 5 R 1 C 1 VIN VOUT F +5V 4 F 3 4 5 n LOW -> Ausgeschaltet GND_P 8 0 VIN VOUT C 0 HIGH -> Eingeschaltet GND_P C 1 FPF1005 1 R315 T302 IO-SW GND_P1 GND_P1 4k7 T_BC817_NPN GND_P Datum Name Bearb. <undefined> <DRAWN> <undefined> Gepr. <TITLE> Norm. 1 1 <COMPANY> Zust. Aenderung Datum Name Datei Name: (Ers.fuer:) (Ers.durch:)
8 Low Side Off PGND RG1_off ParS1 RSense 0.1 D01IN1182 13/23 AN1299 APPLICATION NOTE HIGH SIDE OFF-LOW SIDE TURNED ON Figure 14. The Low side is turned On, the current that flows through the low side switch is
DFN10 (Top View) (Top View) Table 1. PIN DESCRIPTION SOIC 8 PACKAGE Pin Out Name Function 1 HIN High side input 2 LIN Low side input 3 GND Ground reference 4 LO Low side output 5 VCC Low side and logic supply 6 HB High side supply return 7 HO High side output 8 VB High side voltage supply Table 2. PIN DESCRIPTION DFN10 PACKAGE Pin Out Name Function 1 VCC Low side and logic supply 2 HIN High side input 3 LIN Low side input 4 GND Ground reference 5 GND Ground reference 6 LO Low side output 7 NC No Connect 8 HB High side supply return 9 HO High side output 10 VB
a high-side open-load at the dedicated low-side output register (LSx) for the associated output (OUTx). Figure 1-3. High-side Load Configuration VS VS HSx OUTx LSx GND If LSx = 1, then the high-side load is open
destruction of Q1 and Q2. To reduce this effect we must reduce the stray capacitance in the high Side Transformer T1 to the minimum and also install a Common Mode Choke on the primary side of the transformer. See Figure 2. Common Mode T1 Choke High Side Control Control Input High Side Common Pin 16
75 side, DD for display side) Supply Threshold used to detect low-to- Cable high transition relative to supplyide 12.5 % of Low-to-High Threshold VTRIGIL (VCC for cable side,DD for Display 17.5 Supply display
ratings (unless otherwise specified, all pins are referenced to COM). parameter symbol scope unit High-side floating absolute voltage -0.3ÿ275 In VB1,2,3 High-side floating offset voltage, VS1,2,3 VB1,2,3-25ÿVB1,2,3+0.3 In high-side output voltage, VHO1,2,3 VS1,2,3-0.3ÿVB1,2,3+0.3 In low-side supply voltage
A Status of High-Side and Low-Side Switches A; Open Drain Output 8 PWM PWM Input 9 NC Not connected EN /DIAG 10 B B Status of High-Side and Low-Side Switches B; Open Drain Output 11 INB Counter Clockwise Input OUT B,Heat 15, 16, 21 Slug3 Source of High-Side Switch B / Drain of Low-Side Switch B 26, 27, 28 GND A Source of Low-Side Switch A (*) 18, 19, 20 GND Source of Low-Side Switch B (*) B (*) Note: GAD and GBD must be externally connected together 2/
Protect the High Side and the Low Side switches from the high voltage on VOLTAGE the battery line in all configuration for the motor. HIGH SIDE AND LOW SIDE DRIVER Drive the gate of the concerned switch to allow a propDS
high-side switches and power supply voltage Heat-Slug 2 or Heat-Dissipator 10 GH2 Gate of high-side switch 2 11 ST2 Status of high-side switch 2; open Drain output 12 SH2 Source of high-side switch 2 13, 14 SL2 Source of low-side switch 2 15 GL2 Gate of low-side switch 2 16 DL2 Drain of low-side switch 2 Heat-Slug 3 or Heat-Dissipator 18 DL1 Drain of low-side switch 1 Heat-Slug 1 or Heat-Dissipator Bold type: Pin needs power
write data into the selected SID register. This pin is normally connected to the system Read/ Write line. CS (Pin 8) This TTL-level input is a low active chip select which controls data transfers between SID and the microprocessor.
of a high voltage gate driver configured as a half-bridge driver. The IX2113 has independent high-side and low-side referenced output channels, both of which are capable of sourcing and sinking 2A peak current. The floating high-side channel can drive MOSFETs or IGBTs up to 600V from the common reference
high-side switches and power supply voltage Heat-Slug 2 or Heat-Dissipator 10 GH2 Gate of high-side switch 2 11 ST2 Status of high-side switch 2; open Drain output 12 SH2 Source of high-side switch 2 13, 14 SL2 Source of low-side switch 2 15 GL2 Gate of low-side switch 2 16 DL2 Drain of low-side switch 2 Heat-Slug 3 or Heat-Dissipator 18 DL1 Drain of low-side switch 1 Heat-Slug 1 or Heat-Dissipator Bold type: Pin needs power
V CLAMPL Low side zener diode clamp voltage 19.6 20.4 21.6 V ICC5 mA High Side Floating Supply UV BS+ High side well UVLO positive threshold 8.0 8.5 9.0 UV BS- High side well UVLO negative threshold 7.8 8.3 8.8 V UV
Thermistor 17 NU Low−side Emitter Connection − Phase U 18 NV Low−side Emitter Connection − Phase V 19 NW Low−side Emitter Connection − Phase W 20 W Phase W Output / High−side Floating Supply Offset Voltage 22 VBW High−side Floating Supply Voltage − Phase W 26 V Phase V Output / High−side Floating Supply Offset Voltage 28 VBV High−side Floating Supply Voltage − Phase V 32 U Phase U Output / High−side Floating Supply Offset Voltage 34 VBU High−side Floating Supply Voltage − Phase U 38
Unless otherwise specified, all pins areCOMas a reference point) parameter symbol scope unit High side floating absolute voltage V B1,2,3 - 0.3~275 V High Side Floating Offset Voltage V S1,2,3 V B1,2-25~V B1,2+0.3 V High side output voltage VHO1,2,3 V S1,-0.3~V B1,2+0.3 V Low side supply voltage V CC
to the high-side power MOSFET source. SLA 8 8 I Low-side source sense input. Connect to the low-side power MOSFET source. SLB 9 9 I Low-side source sense input. Connect to the low-side power MOSFET source. SLC 16 16
Smart Highside Power Switch BTS 100 TEMPFET Features ● P channel ● Enhancement mode ● Temperature sensor with thyristor characteristic ● The drain pin is electrically shorted to the tab Pin 1 2 3 G D S Type V DS ID R DS(on) Package Ordering Code BTS 100 — 50 V — 8 A 0.3 TO-220AB C67078-A5007-A2 Maximum Ratings Parameter Symbol Values Unit Drain-source voltage VDS — 50 V Drain-gate voltageRGS= 20 k VDGR — 50 Gate-source voltage VGS ± 20 Continuous drain currentC = 30 °C ID — 8.0 A ISO drain current I — 1.5 D-ISO TC = 85 ˚CV GS= 10 V,VDS = 0.5 V Pulsed drain current, T = 25 °C I — 32 C D puls Short
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