if-else Frage in VHDL?

Hallo Leute,

kann mir jemand helfen und erklären wo der Unterschied in einem Prozess 
zwischen ein "if" allein und "if else" ist? wird das signal 
"start_show_disp_data" im ersten Fall nicht gespeichert und im 2ter Fall 
doch schon, oder werden die signale shDD_ready,show_ram davon betroffen?

**************************  1 Fall: nur if  *********
      ...
      if start_show_disp_data = '1' then
        ShDD_ready <= '1';
        show_ram <= '1';
        ShDD_state <= ShDD_ST2 ;
      end if;
      ...
*************************** 2 Fall: if+else *********

      ...
      if start_show_disp_data = '1' then
        ShDD_ready <= '1';
        show_ram <= '1';
        ShDD_state <= ShDD_ST2 ;
      else
        ShDD_ready <= '0';
        show_ram <= '0';
        ShDD_state <= ShDD_ST1 ;
      end if;
      ...






*****************************************************

  SHOWDISPDATA_FSM: process (clock_fpga, reset)
  begin
  if reset='1'  then
     ShDD_state <= ShDD_ST1;
     ShDD_ready <= '0';
     show_ram <= '0';

  elsif rising_edge(clock_fpga) then

    case ShDD_state is
    when ShDD_ST1 => -- warten auf start gegenfalls ready signal setzen
      if start_show_disp_data = '1' then
        ShDD_ready <= '1';
        show_ram <= '1';
        ShDD_state <= ShDD_ST2 ;
      else
        ShDD_ready <= '0';
        show_ram <= '0';
        ShDD_state <= ShDD_ST1 ;
      end if;

    when ShDD_ST2 => -- unmittelbar show_ram = 0;

        ShDD_ready <= '1';
        show_ram <= '0';
        ShDD_state <= ShDD_ST3 ;


    when ShDD_ST3 => -- warten auf Datensignal
      if  cmd_ndata = '0' then
        ShDD_ready <= '0';
        show_ram <= '0';
        ShDD_state <= ShDD_ST1 ;
      elsif  adv_in_ud = '0' or new_command_occured = '1' then
        ShDD_state <= ShDD_ST1 ;
        ShDD_ready <= '0';
        show_ram <= '0';
      end if;

    end case;
  end if;
  end process;

MFG