AX8 mcu in einen Spartan 3E

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- use work.AX_Pack.all;

-- This is the top-level definition, which connects to the

-- I/O pins of the FPGA.

entity fpga_top is

  port(

    CLK_50M   : in STD_LOGIC; -- 50 MHZ clock.

    BTN_NORTH : in STD_LOGIC; -- Use as a reset. Signal is high when pushed.

    -- SW     : inout STD_LOGIC_VECTOR(3 downto 0); -- Switches (port B).

    LED       : out STD_LOGIC_VECTOR(7 downto 0); -- LED's (port D).

    rxd_232   : in STD_LOGIC;  -- Connects to the RS-232 level shifter.

    txd_232   : out STD_LOGIC; -- Connects to the RS-232 level shifter.

    txd_logic : out STD_LOGIC   -- Connects to a digital I/O pin.

  );

end fpga_top;

architecture rtl of fpga_top is

  component A90Smisc port(

    Clk     : in std_logic;

    Reset_n : in std_logic;

    INT0    : in std_logic;

    INT1    : in std_logic;

    T0      : in std_logic;

    T1      : in std_logic;

    ICP     : in std_logic;

    RXD     : in std_logic;

    TXD     : out std_logic;

    OC      : out std_logic;

    Port_B  : inout std_logic_vector(7 downto 0);

    Port_D  : inout std_logic_vector(7 downto 0)

  );

  end component;

  signal int0_val : std_logic := '0';

  signal int1_val : std_logic := '0';

  signal t0_val : std_logic := '0';

  signal t1_val : std_logic := '0';

  signal icp_val : std_logic := '0';

  signal oc_val : std_logic := '0';

  --signal clk_div : std_logic_vector(23 downto 0);

  signal clk_div : std_logic_vector(15 downto 0);

  signal Clk : std_logic;

  signal portb_bits : std_logic_vector(7 downto 0);

  signal portd_bits : std_logic_vector(7 downto 0);

  signal btn_reset : std_logic;

  signal rxd_val : std_logic;

  signal txd_val : std_logic;

begin

  -- Divide the 50MHz master clock by 50, to create a 1MHz

  -- clock for the AX8 core.

  process(CLK_50M) begin

    if rising_edge(CLK_50M) then

      if clk_div = x"0031" then

        clk_div <= x"0000" ;

      else

        clk_div <= clk_div + 1;

      end if;

      if clk_div > x"0018" then

        Clk <= '1';  -- A more symmetric clock.

      else

        Clk <= '0';

      end if;

    end if;

  end process;

  -- Connect the inputs: reset and RS-232.

  btn_reset <= not BTN_NORTH;

  rxd_val <= rxd_232;

  avrchip : A90Smisc port map (

      Clk => Clk,

      Reset_n => btn_reset,

      INT0    => int0_val,

      INT1    => int1_val,

      T0      => t0_val,

      T1      => t1_val,

      ICP     => icp_val,

      RXD     => rxd_val,

      TXD     => txd_val,

      OC      => oc_val,

      Port_B  => portb_bits,

      Port_D  => portd_bits

    );

  -- Connect the outputs.

  LED <= portd_bits;     -- LED's on port D.

  txd_232 <= txd_val;    -- RS-232 output.

  txd_logic <= txd_val;  -- Logic-level copy of the RS-232 signal.

end;