Gast
#1013286
Hey Leute. Ich bin ziemlicher Anfänger in VHDL und FPGA. Ich habe ein Nexysw Board von Digilant und wollte mir nun mal einen einfachen Zähler(finite_state_machine) bauen. es soll einen Asynchrone reset geben um das ganze zu stoppen und auf den Zustando zu bringen wo keine Led leuchtet. nach betätigen des start schalters sollen die 7 LED´s der reihe nach durch leuchten.....also die Zustände hoch zählen. Bei der synthese des Quellcodes kommen mehrere Warnungen: Par:288 - The signal AR_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal clock_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:288 - The signal start_IBUF has no load. PAR will not attempt to route this signal. WARNING:Par:283 - There are 3 loadless signals in this design. This design will cause Bitgen to issue DRC warnings. Was mache ich Grundsätzlich falsch? wie gesagt, bin absoluter Beginner. hier mein Quellcode library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Projekt_1 is Port ( led_1 : out STD_LOGIC; led_2 : out STD_LOGIC; led_3 : out STD_LOGIC; led_4 : out STD_LOGIC; led_5 : out STD_LOGIC; led_6 : out STD_LOGIC; led_7 : out STD_LOGIC; AR : in STD_LOGIC; start : in STD_LOGIC; clock: in STD_LOGIC); end Projekt_1; architecture finite_state_machine of Projekt_1 is signal state: STD_LOGIC_VECTOR(2 downto 0) ; begin process (AR,clock) begin if AR='1' then state <= "000" ; elsif rising_edge(clock) then case state is when "000" => if start = '1' then state <= "001" ; --else state <="000" ; end if; when "001" => state <= "010" ; led_1 <='1'; when "010" => state <= "011" ; led_2 <='1'; when "011" => state <= "100" ; led_3 <='1'; when "100" => state <= "101" ; led_4 <='1'; when "101" => state <= "110" ; led_5 <='1'; when "110" => state <= "111" ; led_6 <='1'; when "111" => state <= "001" ; led_7 <='1'; when others => end case; end if; end process; end finite_state_machine; LG marco